2.2.1. Overview

The block diagram for the clock and reset circuit is shown in Figure 2.4.

Figure 2.4. Clock and reset block diagram

An example of external clock sources for the CPU, memory, and bus clocks is shown in Figure 2.5.

Figure 2.5. External clock signals and clock selection

The clock and reset controller has two modes of operation for driving the processor clocks:

The clock and reset controller generates two clocks for the AHB bridges:

The external part of the three AHB bridges can also be driven by an external clock (HCLKM1 for master 1, HCLKM2 for master 2, or HCLKS for the slave bus) for asynchronous operating mode.

All ARM926PXP development chip clocks, except for the System Controller clock itself (SCLK), are turned off in SLEEP mode.

Using the PLL to de-skew the on-chip clocks with respect to XTALCLKEXT allows synchronous AHB bridges to be used for low latency data transfer across the chip boundary. The XTALCLKEXT frequency must meet the minimum PLL input frequency requirement. The PLL also multiplies XTALCLKEXT to allow the processor clock and AMBA subsystem clocks to be at higher frequencies. As the PLL is the only source of clocks for the processor and AMBA subsystem the frequency cannot be changed during normal operation. The clock ratio between the processor, AMBA subsystem and XTALCLKEXT is fixed after reset. Changes in the System Controller state machine have no affect on the clocks though it can still move through the power management states and application software will be unaffected.

Driving the on-chip clocks from one of three asynchronous off-chip clocks (REFCLK32K, PLLCLKEXT, or XTALCLKEXT) allows the System Controller state machine to select the clock source. The System Controller can switch between clocks running at different speeds as part of a power management strategy. It can also change the processor to AMBA subsystem clock ratio. The on-chip PLL cannot be used to de-skew clocks as the input frequencies may be outside of the PLL specification. The skew between on-chip and off-chip clocks requires asynchronous AHB bridges to be used. The data transfer latency of asynchronous bridges is much higher than that of the synchronous bridges.

In the example shown in Figure 2.5 and with the default clock and configuration values:

The system controller in the ARM926PXP development chip can switch the system into power-saving modes (slow, doze, and sleep).

In the power-saving modes, the external low-frequency clocks are used as CPUCLK. Because of the low-speed external clock, the AHB bridges typically operate in the lower performance asynchronous mode and are controlled by external clocks HCLKM1, HCLKM2, and HCLKS.

The following signals control the internal multiplexors in the ARM926PXP development chip:

CFGPLLBYPASS

Bypasses the PLL and uses XTALCLKEXT as the input to the CPUCLK multiplexor. The default is LOW, the PLL output is used.

CFGUSEPLL

Selects an external clock (REFCLK32K, PLLCLKEXT, or XTALCLKEXT) instead of the PLL output as CPUCLK. The default is HIGH, the output from the PLL multiplexor is used and the power-saving modes are disabled.

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