2.6. Control, configuration, and test signals on pads

This section lists control, configuration, and test signals on the input/output pads.

Note

For details on AHB signals, see Chapter 3 Memory Map and Memory Configuration and Chapter 4 AHB Monitor.

For details on other peripherals and controllers, see the chapter describing the component.

In order to simplify finding signal information, some signals appear in more than one table. For example TCK is in both Table 2.8 and Table 2.9.

Table 2.5 lists the debug signals for the ARM926EJ-S.

Table 2.5. ARM926EJ-S signals

Signal NameTypeDescription
DBGACKOutputDebug acknowledge indicates when the ARM CPU is in debug state (active HIGH).
EDBGRQInputExternal request for ARM to enter debug state (active HIGH).

Table 2.6 lists the ETM signals.

Table 2.6. ETM signals

Signal NameTypeDescription
ETMEXTINInputDebug cross trigger support.
ETMEXTOUT[3:0]OutputDebug cross trigger support.
PIPESTAT[2:0]OutputPipeline status
TRACECLKOutputTrace clock
TRACEPKT[15:0]OutputTrace packet port
TRACESYNCOutputTrace synchronization

Table 2.7 lists the reset and configuration signals.

Table 2.7. Reset and configuration signals

Signal NameTypeDescription

nPORESET

Input

This is an active-LOW power-on reset input used to reset the MPMC refresh timer, System Controller, and the Clock and Reset Controller.

CONFIGDATA[28:0]InputsConfiguration inputs on HDATAM2[28:0] sampled at reconfiguration. (See External configuration signals for details.)

nCONFIGCLR

Input

This resets all of the configuration bits before nPORESET and nRESET are released.

CONFIGINITInputSamples the status of pads to define the configuration signals (rising edge).
nRESETInputSystem reset (active LOW).
TESTSELECTInput

Manufacturing test mode select. This signal is asynchronous and should be static after reset. Signals form the Configuration block and the Clock and Reset Controller are forced to a known state.

Note

This signal is used for manufacturing test only and must always be held LOW.

SCANENABLEInput

Manufacturing test mode scan enable.

Note

This signal is used for manufacturing test only.

BIGENDOUTOutputByte endian mode.

Table 2.8 lists the clock signals.

Table 2.8. Clock signals

ClockDirectionDescription
XTALCLKEXTInputIf the on-chip PLL is used, this input is the reference clock for the PLL. If the on-chip PLL is not used, this input can drive the processor and AMBA subsystem clocks. This clock can be selected from the System Controller.
PLLCLKEXTInputIf the on-chip PLL is not used, this input can drive the processor and AMBA subsystem clocks. This clock can be selected from the System Controller
HCLKM1InputThis input provides an alternative clock source that can be used to time the external part of the M1 bus.
HCLKM2InputThis input provides an alternative clock source that can be used to time the external part of the M2 bus.
HCLKSInputThis input provides an alternative clock source that can be used to time the external part of the S bus.
CLCDCLKEXTInputThis input is used to drive the external interface of the CLCDC.
REFCLK32KInputThis input provides a constantly running slow frequency used to provide a timing reference for the Timer and Watchdog modules at a nominal rate of 32kHz (32 768Hz).
RTC1HZCLKInputThis input is used to clock the RTC timer at a nominal rate of 1Hz.
SCIREFCLKEXTInputThis input is used to drive the external interface of the SCI.
SSPCLKEXTInputThis input is the clock for the SSP external interface.
TIMCLKEXTInputThis input provides an alternative clock source that can be used by the ARM926PXP development chip Timer modules. It must remain constant when the PLL frequency is varied. It is required to provide the Timer modules with at least 10µs resolution and must therefore be at least 100KHz although much higher frequencies can also be used.
UARTCLKEXTInputThis input provides an alternative clock source that can be used to derive the UART baud frequencies.
nPLLRESETInputOn-chip PLL reset (active LOW).
PLLPWRDNInputOn-chip PLL power down (active HIGH).
TCKInputThis input is the JTAG clock
RTCKOutputThis output is the returned JTAG clock
MPMCCLK[4:0]OutputThese are the output clocks from the MPMC.
SMCLK[2:0]OutputThese are the output clocks from the SSMC.
SMFBCLKInputThis input is the feedback clock for the SSMC.

Table 2.9 lists the JTAG signals.

Table 2.9. JTAG TAP signals

Signal NameTypeDescription
TCKInputTest clock.
TMSInputTest mode select.
nTRSTInputTest reset (active LOW).
TDIInputBoundary scan input.
nBSTAPENInputWhen LOW the boundary scan TAP controller is selected. When HIGH the Multi-ICE processor debug interface is selected.
TDOTristate outputBoundary scan output.
RTCKOutputMullet-ICE TCK synchronization.
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