8.3. DMA signals on pads

The pad input and output signals for the DMAC are shown in Table 8.2. These signals are for connection to external DMA capable peripherals.

Table 8.2. DMA request and response signal descriptions

Name

Type

Description

DMACBREQ[5:0]

Input

DMA burst transfer request.

DMACSREQ[5:0]

Input

DMA single transfer request.

DMACLBREQ[5:0]

Input

DMA last burst transfer request.

DMACLSREQ[5:0]

Input

DMA last single transfer request.

DMACLR[5:0]

Output

DMA request acknowledge clear.

DMACTC[5:0]

Output

DMA terminal count. Indicates that the transaction is complete and the packet of data is transferred.

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