5.1. About the CLCDC

The PrimeCell Smart Color LCD Controller PL110 (CLCDC) is an Advanced Microcontroller Bus Architecture (AMBA) compliant System-on-a-Chip (SoC) peripheral that is developed, tested, and licensed by ARM. The CLCDC connects to the AHB bus matrix.

The release version used is PL110 CLCDC r0p0-00alp0. For detailed information on the controller, see the ARM PrimeCell Color LCD Controller (PL110) Technical Reference Manual. The base address for the CLCDC registers is 0x10120000.

The CLCDC performs translation of pixel-coded data into the required formats and timings to drive a variety of single/dual mono and color LCDs.

Support is provided for passive Super Twisted Nematic (STN) and active Thin Film Transistor (TFT) LCD display types.

STN displays

STN display panels require algorithmic pixel pattern generation to provide pseudo gray-scaling on mono, or color creation on color displays.

TFT displays

TFT display panels require the digital color value of each pixel to be applied to the display data inputs.

Packets of pixel coded data are fed using the AMBA AHB interface, to two independent, programmable, 32-bit wide, DMA FIFOs that act as input data flow buffers.

The buffered pixel coded data is then unpacked using a pixel serializer.

Depending on the LCD type and mode, the unpacked data can represent:

In the case of STN displays, either a value obtained from the addressed palette location or the true value is passed to the gray-scaling generators. The hardware coded gray-scale algorithm logic sequences the addressed pixels activity over a programmed number of frames to provide the effective display appearance.

For TFT displays, either an addressed palette value or true color value is passed directly to the output display drivers, bypassing the gray-scaling algorithmic logic.

Besides data formatting, the CLCDC provides a set of programmable display control signals, that include:

The CLCDC uses the external clock source CLCDCLKEXT for timing the pixel clock.

The CLCDC data output can be converted to a VGA display signal by adding an external Digital to Analog Converter (DAC).

There is also a single combined interrupt that is raised when any of the individual interrupts become active. The combined interrupt signal is output to interrupt 16 of the VIC.

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