18.3. VFP9-S system control and status registers

The VFP9-S coprocessor provides sufficient information for processing all exception conditions encountered by the hardware. In an exceptional situation, the hardware provides:

Five VFP9-S registers support exceptional conditions:

These registers are designed to be used with the support code software available from ARM Limited. As a result, this document does not fully specify exception handling in all cases.

In addition, the source data registers for an exceptional instruction are available to the support code. However, some or all of the other data registers in the ARM9E processor and the VFP9-S coprocessor might be modified and not in the state they were in at the time the exceptional instruction was issued.

Access to the FPEXC, FPINST, and FPINST2 registers is possible only in a privileged mode, and does not trigger exceptions. Use the FMRX instruction to store these registers and the FMXR instruction to load them. Table 18.1 describes access to these registers.

Table 18.1. Access to control registers

Register

FMXR/FMRX <reg> field encoding

Exception processing trigger?

Legal modes

FPSID0000NoAny
FPSCR0001NoAny
FPEXC1000

No

Privileged

FPINST1001

No

Privileged

FPINST21010NoPrivileged
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