4.3.14.  CtArmdCastOut<x>

The ARM926 data AHB interface uses the INCR4 burst format, with specific protection bits set, to perform cache writebacks. The writeback can be either full or half cache line writes:

These registers contain the total count of completed cache line writeback transactions that have occurred on the ARM-D AHB layer. The count is disabled by default and can be controlled through the AHBMONCtrlReg, and reset through the AHBMONRstCtrs. The counters are also controlled by the DBGACK in relation to configuration, see AHBMONCtrlReg.

Copyright © 2004, 2006 ARM Limited. All rights reserved.ARM DDI 0287B
Non-Confidential