4.3.2.  Ct<layer>Wr

The write count registers are associated with a AHB layer that contains a master that is write capable.

The registers contain the total count of completed write transfers of all possible burst types that have occurred on the associated AHB layer. The count is disabled by default and can be controlled through the AHBMONCtrlReg, and reset through the AHBMONRstCtrs. The counters associated with the ARM D layer are also controlled by the DBGACK in relation to configuration, see AHBMONCtrlReg.

Copyright © 2004, 2006 ARM Limited. All rights reserved.ARM DDI 0287B
Non-Confidential