ARM926EJ-S Development Chip Reference Manual 4.3. AHB Monitor registers

4.3. AHB Monitor registers

Many of the registers in the AHB monitor replicate behavior over two or more PWP AHB layers. Therefore to minimize verboseness, the behaviors of the registers that overlap are described together. The generic description is referred to by replacing the reference to the specific AHB layer with <layer>:

	Ct<layer>Rd	Ct<layer>Wr	Ct<layer>Rd<x>
	Ct<layer>Wr<x>
	Ct<layer>BurstSingle	Ct<layer>BurstIncr	CtExpBurstWrap4	Ct<layer>BurstIncr4	CtExpBurstWrap8	Ct<layer>BurstIncr8	CtExpBurstWrap16	Ct<layer>BurstIncr16	CtArm<x>LineFill	CtArmdCastOut<x>
	CtArmdPageWalk<x>
	Ct<layer>WaitTotal	Ct<layer>WaitNonSeqSlave	Ct<layer>WaitNonSeqBus	Ct<layer>WaitThresholdHit	<layer>WaitThreshold	CtGxiWr	CtGxiRd	CtGxiWrAddrWait	CtGxiRd<layer>Wait	CtGxiPageCount	CtGxiPageSize	AHBMONRstCtrs	AHBMONPrstCtrs	AHBMONCtrlReg	CtTotalCycles	CtTotalCyclesEn	CtTotalCyclesNonDebug	AHBMONPeriphID	AHBMONPCellID

The AHB Monitor registers are shown in Table 4.14.

Unless specified otherwise, the registers are 32-bit wide counters, read only, and reset to 0x0 on reset.

Table 4.14. AHB Monitor registers

Name	Address	Description
CtArmiRd	`0x101D0000`	Counter. See Ct<layer>Rd.
CtArmiBurstSingle	`0x101D0008`	Counter. See Ct<layer>BurstSingle.
CtArmiBurstIncr4	`0x101D0014`	Counter. See Ct<layer>BurstIncr4.
CtArmiLineFill	`0x101D0040`	Counter. See CtArm<layer>LineFill.
CtArmiWaitTotal	`0x101D0030`	Counter. See Ct<layer>WaitTotal.
CtArmiWaitNonSeqSlave	`0x101D0028`	Counter. See Ct<layer>WaitNonSeqSlave.
CtArmiWaitNonSeqBus	`0x101D002C`	Counter. See Ct<layer>WaitNonSeqBus.
CtArmiWaitThresholdHit	`0x101D0034`	Counter. See Ct<layer>WaitThresholdHit register.
ArmiWaitThreshold	`0x101D0038`	4-bit wide R/W Wait Threshold Register. See <layer>WaitThreshold register.
CtClcdRd	`0x101D0100`	Counter. See Ct<layer>Rd.
CtClcdBurstIncr	`0x101D010C`	Counter. See Ct<layer>BurstIncr.
CtClcdBurstIncr4	`0x101D0114`	Counter. See Ct<layer>BurstIncr4.
CtClcdBurstIncr8	`0x101D011C`	Counter. See Ct<layer>BurstIncr8.
CtClcdBurstIncr16	`0x101D0124`	Counter. See Ct<layer>BurstIncr16.
CtClcdWaitTotal	`0x101D0130`	Counter. See Ct<layer>WaitTotal.
CtClcdWaitNonSeqSlave	`0x101D0128`	Counter. See Ct<layer>WaitNonSeqSlave.
CtClcdWaitNonSeqBus	`0x101D012C`	Counter. See Ct<layer>WaitNonSeqBus.
CtClcdWaitThresholdHit	`0x101D0134`	Counter. See Ct<layer>WaitThresholdHit register.
ClcdWaitThreshold	`0x101D0138`	4-bit wide R/W Wait Threshold Register. See <layer>WaitThreshold register.
CtDma0Rd	`0x101D0200`	Counter. See Ct<layer>Rd.
CtDma0Wr	`0x101D0204`	Counter. See Ct<layer>Wr.
CtDma0RdUart	`0x101D0240`	Counter. See Ct<layer>Rd<x>.
CtDma0WrUart	`0x101D0244`	Counter. See Ct<layer>Wr<x>.
CtDma0RdSci	`0x101D0248`	Counter. See Ct<layer>Rd<x>.
CtDma0WrSci	`0x101D024C`	Counter. See Ct<layer>Wr<x>.
CtDma0RdSsp	`0x101D0250`	Counter. See Ct<layer>Rd<x>.
CtDma0WrSsp	`0x101D0254`	Counter. See Ct<layer>Wr<x>.
CtDma0BurstIncr	`0x101D020C`	Counter. See Ct<layer>BurstIncr.
CtDma0BurstIncr4	`0x101D0214`	Counter. See Ct<layer>BurstIncr4.
CtDma0BurstIncr8	`0x101D021C`	Counter. See Ct<layer>BurstIncr8.
CtDma0BurstIncr16	`0x101D0224`	Counter. See Ct<layer>BurstIncr16.
CtDma0WaitTotal	`0x101D0230`	Counter. See Ct<layer>WaitTotal.
CtDma0WaitNonSeqSlave	`0x101D0228`	Counter. See Ct<layer>WaitNonSeqSlave.
CtDma0WaitNonSeqBus	`0x101D022C`	Counter. See Ct<layer>WaitNonSeqBus.
CtDma0WaitThresholdHit	`0x101D0234`	Counter. See Ct<layer>WaitThresholdHit register.
Dma0WaitThreshold	`0x101D0238`	4-bit wide R/W Wait Threshold Register. See <layer>WaitThreshold register.
CtDma1Rd	`0x101D0300`	Counter. See Ct<layer>Rd.
CtDma1Wr	`0x101D0304`	Counter. See Ct<layer>Wr.
CtDma1BurstIncr	`0x101D030C`	Counter. See Ct<layer>BurstIncr.
CtDma1BurstIncr4	`0x101D0314`	Counter. See Ct<layer>BurstIncr4.
CtDma1BurstIncr8	`0x101D031C`	Counter. See Ct<layer>BurstIncr8.
CtDma1BurstIncr16	`0x101D0324`	Counter. See Ct<layer>BurstIncr16.
CtDma1WaitTotal	`0x101D0330`	Counter. See Ct<layer>WaitTotal.
CtDma1WaitNonSeqSlave	`0x101D0328`	Counter. See Ct<layer>WaitNonSeqSlave.
CtDma1WaitNonSeqBus	`0x101D032C`	Counter. See Ct<layer>WaitNonSeqBus.
CtDma1WaitThresholdHit	`0x101D0334`	Counter. See Ct<layer>WaitThresholdHit register.
Dma1WaitThreshold	`0x101D0338`	4-bit wide R/W Wait Threshold Register. See <layer>WaitThreshold register.
CtExpRd	`0x101D0400`	Counter. See Ct<layer>Rd.
CtExpWr	`0x101D0404`	Counter. See Ct<layer>Wr.
CtExpRdApbDma	`0x101D0454`	Counter. See Ct<layer>Rd<x>.
CtExpWrApbDma	`0x101D0458`	Counter. See Ct<layer>Wr<x>.
CtExpRdApbCore	`0x101D045C`	Counter. See Ct<layer>Rd<x>.
CtExpWrApbCore	`0x101D0460`	Counter. See Ct<layer>Wr<x>.
CtExpBurstSingle	`0x101D0408`	Counter. See Ct<layer>BurstSingle.
CtExpBurstIncr	`0x101D040C`	Counter. See Ct<layer>BurstIncr.
CtExpBurstWrap4	`0x101D0410`	Counter. See Ct<layer>BurstIncr4.
CtExpBurstIncr4	`0x101D0414`	Counter. See Ct<layer>BurstIncr4.
CtExpBurstWrap8	`0x101D0418`	Counter. See CtExpBurstWrap8.
CtExpBurstIncr8	`0x101D041C`	Counter. See Ct<layer>BurstIncr8.
CtExpBurstWrap16	`0x101D0420`	Counter. See CtExpBurstWrap16.
CtExpBurstIncr16	`0x101D0424`	Counter. See Ct<layer>BurstIncr16.
CtExpWaitTotal	`0x101D0430`	Counter. See Ct<layer>WaitTotal.
CtExpWaitNonSeqSlave	`0x101D0428`	Counter. See Ct<layer>WaitNonSeqSlave.
CtExpWaitNonSeqBus	`0x101D042C`	Counter. See Ct<layer>WaitNonSeqBus.
CtExpWaitThresholdHit	`0x101D0434`	Counter. See Ct<layer>WaitThresholdHit register.
CtExpWaitThreshold	`0x101D0438`	4-bit wide R/W Wait Threshold Register. See <layer>WaitThreshold register.
CtArmdRd	`0x101D0500`	Counter. See Ct<layer>Rd.
CtArmdWr	`0x101D0504`	Counter. See Ct<layer>Wr.
CtArmdRdApbDma	`0x101D0554`	Counter. See Ct<layer>Rd<x>.
CtArmdWrApbDma	`0x101D0558`	Counter. See Ct<layer>Wr<x>.
CtArmdRdApbCore	`0x101D055C`	Counter. See Ct<layer>Rd<x>.
CtArmdWrApbCore	`0x101D0560`	Counter. See Ct<layer>Wr<x>.
CtArmdBurstSingle	`0x101D0508`	Counter. See Ct<layer>BurstSingle.
CtArmdBurstIncr4	`0x101D0514`	Counter. See Ct<layer>BurstIncr4.
CtArmdBurstIncr8	`0x101D051C`	Counter. See Ct<layer>BurstIncr8.
CtArmdLineFill	`0x101D0540`	Counter. See CtArm<layer>LineFill.
CtArmdCastOut4	`0x101D0544`	Counter. See CtArmdCastOut<x>.
CtArmdCastOut8	`0x101D0548`	Counter. See CtArmdCastOut<x>.
CtArmdPageWalkD	`0x101D054C`	Counter. See CtArmdPageWalk<x>.
CtArmdPageWalkI	`0x101D0550`	Counter. See CtArmdPageWalk<x>.
CtArmdWaitTotal	`0x101D0530`	Counter. See Ct<layer>WaitTotal.
CtArmdWaitNonSeqSlave	`0x101D0528`	Counter. See Ct<layer>WaitNonSeqSlave.
CtArmdWaitNonSeqBus	`0x101D052C`	Counter. See Ct<layer>WaitNonSeqBus.
CtArmdWaitThresholdHit	`0x101D0534`	Counter. See Ct<layer>WaitThresholdHit register.
CtArmdWaitThreshold	`0x101D0538`	Wait Threshold Register. See <layer>WaitThreshold register.
CtGxiWr	`0x101D0604`	Counter. See Ct<layer>Wr.
CtGxiRd	`0x101D0600`	Counter. See Ct<layer>Rd.
CtGxiWrAddrWait	`0x101D0610`	Counter. See Ct<layer>Wr<x>.
CtGxiRdAddrWait	`0x101D0620`	Counter. See Ct<layer>Rd<x>.
CtGxiRdDataWait	`0x101D0630`	Counter. See Ct<layer>Rd<x>.
CtGxiWrAWaitThresholdHit	`0x101D0614`	Counter. See Ct<layer>Wr<x>.
CtGxiWrAWaitThreshold	`0x101D0618`	4-bit wide R/W Wait Threshold Register. See Ct<layer>Wr<x>.
CtGxiRdAWaitThresholdHit	`0x101D0624`	Counter. See Ct<layer>Rd<x>.
CtGxiRdAWaitThreshold	`0x101D0628`	4-bit wide R/W Wait Threshold Register. See <layer>WaitThreshold register.
CtGxiRdDWaitThresholdHit	`0x101D0634`	Counter. See Ct<layer>Rd<x>.
CtGxiRdDWaitThreshold	`0x101D0638`	4-bit wide R/W Wait Threshold Register. See Ct<layer>Rd<x>.
CtGxiPageChange	`0x101D0608`	Counter. See CtGxiPageChange.
CtGxiPageSize	`0x101D0E08`	2-bit Read-only register that selects page size used by the page change counter. See GxiPageSize.
CtTotalCycles	`0x101D0700`	Value of a counter of bus cycles. See CtTotalCycles.
CtTotalCyclesEn	`0x101D0704`	Value of a counter of bus cycles. See CtTotalCyclesEn.
CtTotalCyclesNonDebug	`0x101D0708`	Value of a counter of bus cycles. See CtTotalCyclesNonDebug.
AHBMONRstCtrs	`0x101D0E00`	Counter reset register. See AHBMONRstCtrs. Write-only.
AHBMONCtrlReg	`0x101D0E04`	3-bit R/W Monitor control register. See AHBMONCtrlReg. Reset value is `0x0`.
AHBMONPeriphID0-3	`0x101D0FE0`	Peripheral identification registers Read-only value `0x00041000`. See AHBMONPeriphID 0 to 3.
AHBMONPCellID0-3	`0x101D0FF0`	PrimeCell identification registers. See AHBMONPCellID. Read-only value is `0xB105F00D`.

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