4.3.18.  Ct<layer>WaitNonSeqBus

The NONSEQ bus wait count registers are associated with a specific AHB layer:

These registers contain the total count of wait states incurred on the first transfer of a burst caused by the bus infrastructure on the associated AHB layer. The count is disabled by default. It can be controlled through AHBMONCtrlReg and reset through AHBMONRstCtrs.

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