4.3.8.  Ct<layer>BurstIncr4

The INCR4 burst count registers are associated with a specific AHB layer that contains a master that is capable of this burst format:

These registers contain the total count, read + write, of completed INCR4 burst transfers that have occurred on the associated AHB layer. The count is disabled by default and can be controlled through the AHBMONCtrlReg, and reset through the AHBMONRstCtrs. The counters associated with the ARM D and ARM I layers are also controlled by the DBGACK in relation to configuration, see AHBMONCtrlReg.

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