13.3. SSMC signals on pads

Table 13.2 describes the signals to the input/output pads.

Table 13.2. Pad signals

Signal name

Direction

Description

nSMBURSTWAIT[0]InputSynchronous burst wait input used by the external device to delay a synchronous burst transfer.
SMBLS7POLInput

This is used to define the reset value of bit 6 in SMBCR7 (nSMBLS):

0 = nSMBLS is active low (default)

1 = nSMBLS is active high.

SMCANCELWAIT

Input

This signal enables the system to recover from an externally waited transfer that takes longer than expected to finish. Active HIGH.

SMDATAIN[31:0]

Input

External input data bus used to read data from memory bank.

SMDATAOUT[31:0]

Input

External output data used to write data from SSMC to memory bank.

SMFBCLKInputThe feedback clock from the memory devices.

SMMWCS7[1:0]

Input

These static configuration bits indicate the memory width used for boot memory bank one:

00 = 8-bit

01 = 16-bit

10 = 32-bit

11 = reserved.

SMWAIT

Input

Wait mode input from external memory controller. Active HIGH or active LOW (default), as programmed in the SSMC control registers for each bank.

nSMCS0

Output

Chip select for bank 0 of external memory, default active LOW.

nSMCS1

OutputChip select for bank 1of external memory, default active LOW.

nSMCS2

Output

Chip select for bank 2 of external memory, default active LOW.

nSMCS3

Output

Chip select for bank 3 of external memory, default active LOW.

nSMCS4

OutputChip select for bank 4 of external memory, default active LOW.

nSMCS5

OutputChip select for bank 5 of external memory, default active LOW.

nSMCS6

Output

Chip select for bank 6 of external memory, default active LOW.

nSMCS7

Output

Chip select for bank 7 of external memory, default active LOW.

nSMDATAEN[3:0]

Output

Tristate input/output pad enable for the byte lanes of the external memory data bus SMDATA[31:0], active LOW. Enables the byte lanes [31:24], [23:16], [15:8], and [7:0] of the data bus independently.

nSMOEN

Output

Output enable for external memory banks, active LOW.

nSMWEN

Output

Write enable for the external memory banks, active LOW.

SMADDR[25:0]

Output

External memory address bus, to external memory banks.

SMADDRVALIDOutputExternal address valid output, used to indicate when the address output is stable during synchronous burst transfers.
SMBAAOutputExternal burst address advance signal. Used to advance the address count in the external memory device.

nSMBLS[3:0]

Output

Byte lane select signals, active LOW. The signals nSMBLS[3:0] select byte lanes [31:24], [23:16], [15:8], and [7:0] on the data bus.

SMCLK[3:0]OutputThe clocks output to synchronous memory devices.
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