C.2. AHB bus timing

Table C.1 lists the timing for the AHB buses. (The bus clock frequency is typically 35MHz for a tcyc of 28.5ns).

Table C.1. ARM926PXP development chip bus timing

Bus signalsClocktovtohtistih
HRESETn inputXTALCLKEXT--10ns2ns
AHB M1 outputs in synchronous mode (HADDR, HSELx, HWRITE, HTRANS[1:0], HSIZE[2:0], HBURST[2:0], and write data)XTALCLKEXT16ns1ns--
AHB M1 inputs in synchronous mode (HREADY, HRESP, HLOCK, and read data)XTALCLKEXT--17ns0ns
AHB M1 outputs in async mode (HADDR, HSELx, HWRITE, HTRANS[1:0], HSIZE[2:0], HBURST[2:0], and write data)HCLKM118ns4ns--
AHB M1 inputs in async mode (HREADY, HRESP, HLOCK, and read data)HCLKM1--17ns4.5ns
AHB M2 outputs in synchronous mode (HADDR, HSELx, HWRITE, HTRANS[1:0], HSIZE[2:0], HBURST[2:0], and write data)XTALCLKEXT16ns1ns--
AHB M2 inputs in synchronous mode (HREADY, HRESP, HLOCK, and read data)XTALCLKEXT--17ns0ns
AHB M2 outputs in async mode (HADDR, HSELx, HWRITE, HSIZE[2:0], HBURST[2:0], and write data)HCLKM218ns4ns--
AHB M2 inputs in async mode (HREADY, HRESP, HLOCK, and read data)HCLKM2--17ns4.5ns
AHB S outputs in synchronous mode (HREADY, HRESP, HLOCK, and read data)XTALCLKEXT16ns1ns--
AHB S inputs in synchronous mode (HADDR, HSELx, HWRITE, HTRANS[1:0], HSIZE[2:0], HBURST[2:0], and write data)XTALCLKEXT--17ns0ns
AHB S outputs in async mode (HREADY, HRESP, HLOCK, and read data)HCLKS18ns4ns--
AHB S inputs in async mode (HADDR, HSELx, HWRITE, HTRANS[1:0], HSIZE[2:0], HBURST[2:0], and write data)HCLKS--17ns4.5ns
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