C.1. About the timing parameters

Figure C.1 shows the parameters that define the setup and hold times. For more detail on timing and example waveforms, see the TRM for the peripheral.

Figure C.1. AC timing example

The following timing parameters are used:

tcyc

The maximum cycle time for the clock signal.

tov

The maximum delay from the relevant clock edge until the ARM926PXP development chip outputs are valid.

toh

The minimum time after the relevant clock edge that the ARM926PXP development chip outputs remain valid.

tis

The minimum time that the ARM926PXP development chip inputs must be valid before the edge of relevant clock.

tih

The minimum time that the ARM926PXP development chip inputs must remain valid after the edge of relevant clock.

Note

For the specifications in this appendix, the rising clock edge is the reference edge unless specified otherwise.

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