19.2. Functional description

Figure 19.1 shows a simplified block diagram of the Watchdog module.

Figure 19.1. Simplified block diagram

The Watchdog module is based around a 32-bit down counter that is initialized from the Reload Register, WdogLoad. The counter decrements by one on each positive clock edge of WDOGCLK when the clock enable WDOGCLKEN is HIGH. When the counter reaches zero, an interrupt is generated. On the next enabled WDOGCLK clock edge the counter is reloaded from the WdogLoad Register and the count down sequence continues. If the interrupt is not cleared by the time that the counter next reaches zero then the Watchdog module asserts the reset signal, WDOGRES, and the counter is stopped.

WDOGCLK can be equal to or be a sub-multiple of the PCLK frequency. However, the positive edges of WDOGCLK and PCLK must be synchronous and balanced.

The Watchdog module interrupt and reset generation can be enabled or disabled as required by use of the Control Register, WdogControl. When the interrupt generation is disabled then the counter is stopped. When the interrupt is re-enabled then the counter starts from the value programmed in WdogLoad, and not from the last count value.

Write access to the registers in the Watchdog module can be disabled by the use of the Watchdog module Lock Register, WdogLock. Writing a value of 0x1ACCE551 to the register enables write accesses to all of the other registers. Writing any other value disables write accesses to all registers except the Lock Register. This feature protects the Watchdog module registers from being spuriously changed by runaway software that might otherwise disable the Watchdog module operation.

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