14.1. About the ARM PrimeCell SSP (PL022)

The PrimeCell Synchronous Serial Port (SSP) is an Advanced Microcontroller Bus Architecture (AMBA) slave block that connects to the DMA APB. The PrimeCell SSP is an AMBA compliant System-on-Chip (SoC) peripheral that is developed, tested, and licensed by ARM.

The release version used is PL022 SSP REL1v2. The base address for the SSP control registers is 0x101F4000. For more information on the controller, see the ARM PrimeCell Synchronous Serial Port Controller (PL022) Technical Reference Manual.

The PrimeCell SSP is a master or slave interface that enables synchronous serial communication with slave or master peripherals having one of the following:

In both master and slave configurations, the PrimeCell SSP performs:

Interrupts are generated to:

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