1.3.1. External memory support

Two memory interfaces are provided to support external static memory and external SDRAM. When modeling high-performance systems, both memory interfaces can be used in parallel. In this configuration, the Synchronous Static Memory Controller PrimeCell PL093 drives the static memory interface and the Multiport Memory Controller PrimeCell GX175 drives the SDRAM memory interface.

When modeling a relatively low-performance system, one memory interface can be used. In this configuration, the Multiport Memory Controller PrimeCell GX175 drives both the static memory and the SDRAM memory interfaces.

The MPMC supports seven ports:

The mapping between the ARM926PXP development chip AHB buses and the MPMC ports is listed in Table 1.1.

Table 1.1. MPMC port allocation

ARM926PXP development chip AHB

MPMC port

CLCDC AHB (highest priority)

Port 0


Port 1


Port 2


Port 3

ARM Instruction AHB

Port 4


Port 5

The SSMC is not a multiport device. However, the AHB bus switch selects one of the following buses for the SSMC:

The MPMC and SSMC have additional AHB control ports that are used to access the configuration registers. These ports are only accessible using the ARM Data AHB bus.

Default memory map

The default memory map is divided into the regions shown in Figure 1.3. They are configured as follows:

  • SDRAM for CS0 and 1 are mapped into a 256Mb region starting at 0x00000000

  • SDRAM for CS2 and 3 are mapped into a 256Mb region starting at 0x70000000

  • the first set of four SSMC banks for CS4, CS5, CS6, and CS7 are mapped into a 256Mb region starting at 0x20000000

  • the second set of four SSMC banks for CS0, CS1, CS2, and CS3 are mapped into a 256Mb region starting at 0x30000000.

The remaining peripheral interfaces are contained in a single 1Mb region, with the AHB peripherals at the bottom of the region and the APB peripherals at the top. This enables either type of peripheral to be added to the region.


The remainder of the address map is decoded by an off-chip AHB bridge and is provided for peripherals external to the ARM926PXP development chip. Because these address regions are not decoded in the ARM926PXP development chip, valid AHB responses must be generated through the external AHB interfaces to any access to an undefined address region.

See Chapter 3 Memory Map and Memory Configuration for more information on the AHB buses and the memory map.

Figure 1.3. Default system bus memory map for ARM DATA AHB bus

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