1.2. Functional description

The ARM926PXP development chip comprises the following functional blocks:

ARM926EJ-S

This is a cached ARM CPU including Instruction and Data caches, Memory Management Unit (MMU), and Tightly Coupled Memory (TCM). It supports the JazelleTM extensions for Java acceleration.

The ARM926EJ-S processor used with the ARM926PXP development chip is configured with 32KB instruction and data caches and 32KB TCMs.

The release version used is ARM926EJ-S r0p3-00rel0. The PrimeXsys Wireless Platform version is r2p0.

For more information on the ARM926EJ-S, see the ARM926EJ-S Technical Reference Manual.

MOVE coprocessor

The MOVE coprocessor is a video encoding acceleration coprocessor designed to accelerate Motion Estimation (ME) algorithms within block-based video encoding schemes such as MPEG4 and H.263. This is done by providing support for the execution of Sum of Absolute Differences (SAD) calculations, which account for most of the processing activity within an ME algorithm. These algorithms require many comparisons between 8x8 pixel blocks to made between a current frame and a reference frame.

The release version used is MOVE r3p0-00bet0.

For more information on the MOVE coprocessor, see the ARM MOVE Coprocessor Technical Reference Manual and Chapter 6 MOVE Coprocessor.

VFP9 coprocessor

The VFP9-S coprocessor is an implementation of the Vector Floating-Point architecture version 2 (VFPv2) and provides floating-point computation that is fully compliant with the ANSI/IEEE Std 754-1985, IEEE Standard for Binary Floating-Point Arithmetic. The VFP9-S coprocessor supports all addressing modes described in section C5 of the ARM Architecture Reference Manual.

The release version used is VFP9-S r1p1.

For more information on the VFP9 coprocessor, see the ARM VFP9-S Coprocessor Technical Reference Manual and Chapter 18 ARM Vector Floating Point Coprocessor (VFP9).

AHB Monitor

The AHB Monitor block outputs transaction information for the buses in the ARM926PXP development chip and is used to evaluate performance and bandwidth utilization analysis.

For more information on the AHB monitor, see Chapter 4 AHB Monitor.

MBX Graphics Accelerator

The ARM MBX HR-S is a graphics accelerator that operates on 3D scene data. Triangles are written directly to the Tile Accelerator on a First In First Out (FIFO) basis so that the CPU is not stalled.

The release version used is MBX HR-S r1p2.

For more information on the MBX accelerator, see the ARM MBX HR-S Graphics Core Technical Reference Manual and Chapter 7 MBX HR-S Graphics Accelerator.

System Controller

This provides a control interface for clock generation components external to the chip. It also controls system-wide and peripherals-specific energy management features.

The release version used is SP810 SYSCTRL r0p0-00ltd0.

For more information on the system controller, see the ARM PrimeCell System Controller (SP810) Technical Reference Manual and Chapter 2 System Controller and Configuration Logic.

Multi-Port Memory Controller (MPMC)

The MPMC can be used to interface with Synchronous Dynamic Random Access Memory (SDRAM) and static memory devices.

The release version used is GX175 MPMC r0p0-00alp2.

For more information on the MPMC, see the ARM Multiport Memory Controller (GX175) Technical Reference Manual and Chapter 10 Multi-Port Memory Controller (MPMC).

Synchronous Static Memory Controller (SSMC)

The SSMC interfaces to off-chip static memory devices such as Read Only Memory (ROM), Static Random Access Memory (SRAM), or static flash memory.

The release version used is PL093 SSMC r0p0-00ltd0.

For more information on the SSMC, see the ARM PrimeCell Static Memory Controller (PL093) Technical Reference Manual and Chapter 13 Synchronous Static Memory Controller (SSMC).

Direct Memory Access Controller (DMAC)

Direct memory access can be used with DMA peripherals. FIFO fill and empty requests from these peripherals can be serviced immediately by the DMAC without CPU interaction. Memory-to-memory DMA is also supported.

The release version used is PL080 DMAC REL1v1.

For more information on DMA, see the ARM PrimeCell DMA (PL080) Technical Reference Manual and Chapter 8 Direct Memory Access Controller (DMAC).

Vectored Interrupt Controller (VIC)

The VIC enables the interrupt handler software to quickly dispatch interrupt service routines in response to peripheral interrupts.

The release version used is PL190 VIC 1v1.

For more information on the VIC, see the ARM PrimeCell Vector Interrupt Controller (PL190) Technical Reference Manual and Chapter 17 Vectored Interrupt Controller (VIC).

Embedded Trace Macrocell (ETM9)

The ETM9 provides a trace port for real-time debug.

The release version used is ETM9 Rev2a. The ETM configuration for the ARM926PXP development chip is Medium-Plus.

For more information on the ETM9, see the ETM9 Technical Reference Manual.

Real Time Clock (RTC)

The RTC provides a one-second resolution clock. This keeps time when the ARM926PXP development chip is inactive and can be used to wake the chip up when a programmed alarm time is reached.

The release version used is PL031 RTC 1v0.

For more information on the RTC, see the ARM PrimeCell Real Time Clock Controller (PL031) Technical Reference Manual and Chapter 11 Real-Time Clock (RTC).

Timer modules

The ARM926PXP development chip provides two Timer modules. They can be used to, for example, generate periodic and timed interrupts required by operating system services.

The release version used is SP804 TIMER r1p0-02ltd0.

For more information on the timers, see the ARM Dual-Timer Module (SP804) Technical Reference Manual and Chapter 15 Dual Timer/Counters.

Watchdog module

This is used to trigger a system reset in the event of software failure.

The release version used is SP805 WDOG r1p0-02ltd0.

For more information on the Watchdog monitor, see the ARM PrimeCell Watchdog Controller (SP805) Technical Reference Manual and Chapter 19 Watchdog Timer.

Universal Asynchronous Receiver-Transmitter (UART)

There are three UARTs in the ARM926PXP development chip. The UARTs perform serial-to-parallel conversion on data received from a peripheral device

The release version used is PL011 UART 1v3.

For more information on the UARTs, see the ARM PrimeCell UART (PL011) Technical Reference Manual and Chapter 16 UART Controller.

Synchronous Serial Port (SSP)

The PrimeCell SSP is a master or slave interface that enables synchronous serial communication with slave or master peripherals having one of the following:

  • a Motorola SPI-compatible interface

  • a Texas Instruments synchronous serial interface

  • a National Semiconductor Microwire interface.

The release version used is PL022 SSP REL1v2.

For more information on the SSP, see the ARM PrimeCell Synchronous Serial Port Controller (PL022) Technical Reference Manual and Chapter 14 Synchronous Serial Port (SSP).

Color Liquid Crystal Display Controller (CLCDC)

The CLCDC performs translation of pixel-coded data into the required formats and timings to drive a variety of single/dual mono and color LCDs. Support is provided for passive Super Twisted Nematic (STN) and active Thin Film Transistor (TFT) LCD display types.

The release version used is a modified PL110 CLCDC r0p0-00alp0 with the hardware cursor from the PL111.

For more information on the CLCDC, see the ARM PrimeCell Color LCD Controller (PL110) Technical Reference Manual and Chapter 5 Color LCD Controller (CLCDC).

General Purpose Input/Output (GPIO) interface

There are four GPIO interfaces in the ARM926PXP development chip. Each GPIO interface provides eight programmable inputs or outputs.

The release version used is PL061 GPIO 1v0.

For more information on the GPIOs, see the ARM PrimeCell GPIO (PL061) Technical Reference Manual and Chapter 9 General Purpose Input Output (GPIO).

Smart Card Interface (SCI)

This connects to smart card, Security Identity Module (SIM) card, and other modules.

The release version used is PL131 SCI 1v0.

For more information on the SCI, see the ARM PrimeCell Smart Card Interface (PL131) Technical Reference Manual and Chapter 12 Smart Card Interface (SCI).

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