| Copyright © 2004, 2006 ARM Limited. All rights reserved. | ARM DDI 0287B |
| Non-Confidential | |
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| Home > Controllers and Peripherals > UART Controller > Functional description > Registers |
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| Home > Controllers and Peripherals > UART Controller > Functional description > Registers |
There are three PrimeCell UARTs in the ARM926PXP development chip. The base addresses are:
0x101F1000.
0x101F2000.
0x101F3000.
The following locations are reserved, and must not be used during normal operation:
locations at offsets 0x008–0x014, and 0x01C are
reserved and must not be accessed
locations at offsets 0x04C–0x07C are
reserved for possible future extensions
locations at offsets 0x080–0x08C are
reserved for test purposes
locations at offsets 0x90–0xFCC are
reserved for future test purposes
location used at offsets 0xFD0–0xFDC are
used for future identification registers
location used at offsets 0xFE0–0xFFC are
used for identification registers.
The following key parameters are programmable:
communication baud rate, integer, and fractional parts
number of data bits
number of stop bits
parity mode
FIFO enable (16 deep) or disable (1 deep)
FIFO trigger levels selectable between 1/8, 1/4, 1/2, 3/4, and 7/8.
internal nominal 1.8432MHz clock frequency (1.42–2.12MHz) to generate low‑power mode shorter bit duration
hardware flow control.
Additional test registers and modes are implemented for integration testing.
| Copyright © 2004, 2006 ARM Limited. All rights reserved. | ARM DDI 0287B |
| Non-Confidential | |
| PDF version | |
| Home > Controllers and Peripherals > UART Controller > Functional description > Registers |