16.2.2. Registers

There are three PrimeCell UARTs in the ARM926PXP development chip. The base addresses are:

UART0

0x101F1000.

UART1

0x101F2000.

UART3

0x101F3000.

The following locations are reserved, and must not be used during normal operation:

Programmable parameters

The following key parameters are programmable:

  • communication baud rate, integer, and fractional parts

  • number of data bits

  • number of stop bits

  • parity mode

  • FIFO enable (16 deep) or disable (1 deep)

  • FIFO trigger levels selectable between 1/8, 1/4, 1/2, 3/4, and 7/8.

  • internal nominal 1.8432MHz clock frequency (1.42–2.12MHz) to generate low‑power mode shorter bit duration

  • hardware flow control.

Additional test registers and modes are implemented for integration testing.

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