3.1.4. AHB bus interfaces

This section describes the AHB bridges that forms part of the ARM926EJS PrimeXsys Platform Development Chip multi-layer AHB system.

Off-chip (master) bridges

The off-chip AHB bridges are AMBA compliant bridges that allows AHB masters in the ARM926EJ-S PXP subsystem to access off-chip AHB slave peripherals. The off-chip AHB bridge has the following features:

  • AMBA compliant AHB slave and master interfaces.

  • Synchronous and asynchronous operation.

  • Pass-through mode for cycle accurate modeling.

  • Tristate pin control for multi-master AHB systems off-chip.

The block diagrams for the off-chip bus interfaces (M1 and M2) are shown in Figure 3.2 and Figure 3.3.

Figure 3.2. AHB M1 interface

Figure 3.3. AHB M2 interface

The bridge AHB master output signals drive the pads of the chip through tristate buffers. As the AHB read and write data buses are never active at the same time, the two are combined onto one set of pads. Tristate buffers allow the write data bus to drive the external AHB data bus. The action of the tristate buffers allows multiple AHB masters to drive the off-chip AHB bus under the control of an external arbiter. The AHB arbiter output signals do not use tristate buffers.

The bridge slave interface is part of the memory map and it will respond to transactions in the appropriate address range. The address input of the slave interface is a full 32-bit address, even though it responds to a decoded address range as it is passed through the bridge unchanged. No address translation is performed. This links the on-chip and off-chip AHB busses and preserves the on-chip address map.

Transactions initiated by the on-chip AHB masters are passed from the slave interface to the master interface of the bridge. The response of off-chip peripherals is then passed back through the bridge. The response of the bridge is dependent on the clock arrangement between the two AHB busses and response of the off-chip peripheral. The bridge will always ensure that AMBA AHB protocols are observed on both AHB busses. To ensure this the slave interface can generate wait states and the master interface can insert BUSY cycles.

A system design outside of the ARM926PXP development chip might break the AHB protocol. If fixed length bursts are broken by an arbiter on the transfer source side of the bridge, an incomplete burst appears on the destination side of the bridge. To avoid breaking the AHB protocol, set the configuration signals CFGINCOVERRIDEM1 and CFGINCOVERRIDEM1 HIGH. All burst information will be converted to INCR. If this situation cannot be encountered due to the system design, fixed length bursts can be passed across the bridges (set CFGINCOVERRIDEM1 and CFGINCOVERRIDEM1 LOW).

The bridge can operate in four modes that define the relationship between the on-chip and off-chip AHB bus clocks and the response of the bridge to AHB transfers. These modes are:

  • Synchronous 1:1 bridge

  • Synchronous N:1 bridge

  • Asynchronous bridge

  • Pass-through bridge.

The multiplexor control determines which of the bridge clocking modes is to be used as shown in Table 3.1.

Table 3.1. On-chip bridge selection

CFGAHBASYNCCFGHCLKEXTDIVSEL[2:0]CFGAHBPASSTBRIDGESEL[1:0]Bridge selected
1xxxx00Asynchronous
0001-111x01Synchronous N:1
0000010Synchronous 1:1
0000111Pass-through

The synchronous 1:1 bridge mode requires that the on-chip and off-chip AHB bus clocks run at the same frequency. The bridge is only provided with the on-chip bus clock. The maximum frequency of the on chip bus clock is restricted by the off-chip bus timing. The paths between the slave and master interfaces of the bridge are registered to provide timing isolation. Registering the AHB signals means that accesses through the bridge incur delays.

The synchronous N:1 bridge mode requires that the on-chip bus clock to runs at an integer multiple of the off-chip AHB bus clock. The bridge is provided with the on-chip bus clock and a clock enable signal. The clock enable indicates which clock edges are valid for the off-chip bus. The maximum frequency of each bus clock is restricted by the timing for that bus and the requirement that the on-chip bus clock must run at an integer multiple of the off-chip bus clock. The paths between the slave and master interfaces of the bridge are registered to provide timing isolation. Registering the AHB signals means that accesses through the bridge incur delays.

The asynchronous bridge mode allows the on-chip and off-chip AHB bus clocks to run at completely independent frequencies. The bridge is provided with two clocks. The maximum frequency of each bus clock is only restricted by the timing for that bus. The paths between the slave and master interfaces of the bridge are registered in both clock domains to provide timing isolation. The registering of the AHB signal paths in both clock domains mean that the bridge will add several clock cycles delay to transactions.

The pass-through bridge mode requires that the on-chip and off-chip AHB bus clocks to run at the same frequency. The bridge is only provided with the on-chip bus clock. The maximum frequency of the on-chip AHB bus clock is limited by the timing of signal paths off and on the chip. The paths between the slave and master interfaces of the bridge are combinatorial. As there are no registers in the AHB signal paths, the bridge will not add any delay to a transaction. This mode is designed for cycle accurate modeling of on-chip masters accessing off-chip slaves.

On-chip (slave) bridge

This section describes the AHB bridge to on-chip peripherals that forms part of the ARM926EJS PrimeXsys Platform Development Chip multi-layer AHB system. The on-chip AHB bridge is an AMBA compliant bridge that allows off-chip AHB masters to access AHB slave peripherals in the ARM926EJ-S PXP subsystem. The on-chip AHB bridge has the following features:

  • AMBA compliant AHB slave and master interfaces

  • Synchronous and asynchronous operation

  • Pass-through mode for cycle accurate modeling

  • Tristate pin control for multi-slave AHB systems off-chip.

The bridge slave interface is part of the off-chip AHB memory map and it will respond to transactions in the appropriate address range. The address input of the slave interface is a full 32-bit address, even though it responds to a decoded address range as it is passed through the bridge unchanged. No address translation is performed. This links the on-chip and off-chip AHB busses and preserves the on-chip address map.

Transactions initiated by the off-chip AHB masters are passed from the slave interface to the master interface of the bridge. The response of on-chip peripherals is then passed back through the bridge. The response of the bridge is dependent on the clock arrangement between the two AHB busses and response of the on-chip peripheral. The bridge will always ensure that AMBA AHB protocols are observed on both AHB busses. To ensure this the slave interface can generate wait states and the master interface can insert BUSY cycles.

A system design outside of the ARM926PXP development chip might break the AHB protocol. If fixed length bursts are broken by an arbiter on the transfer source side of the bridge, an incomplete burst appears on the destination side of the bridge. To avoid breaking the AHB protocol, set the configuration signals CFGINCOVERRIDES and CFGINCOVERRIDES HIGH. All burst information will be converted to INCR. If this situation cannot be encountered due to the system design, fixed length bursts can be passed across the bridges (set CFGINCOVERRIDES and CFGINCOVERRIDES LOW).

The bridge can operate in four modes that define the relationship between the on-chip and off-chip AHB bus clocks and the response of the bridge to AHB transfers. These modes are:

  • Synchronous 1:1 bridge

  • Synchronous N:1 bridge

  • Asynchronous bridge

  • Pass-through bridge.

The synchronous 1:1 bridge mode requires that the on-chip and off-chip AHB bus clocks to run at the same frequency. The bridge is only provided with the on-chip bus clock. The maximum frequency of the on chip bus clock is restricted by the off-chip bus timing. The paths between the slave and master interfaces of the bridge are registered to provide timing isolation. Registering the AHB signals means that accesses through the bridge incur delays.

The multiplexor control determines which of the bridge clocking modes is to be used as shown in Table 3.1.

The synchronous 1:N bridge mode requires that the on-chip bus clock runs at an integer multiple of the off-chip AHB bus clock. The bridge is provided with the on-chip bus clock and a clock enable signal. The clock enable indicates which clock edges are valid for the off-chip bus. The maximum frequency of each bus clock is restricted by the timing for that bus and the requirement that the on-chip bus clock must run at an integer multiple of the off-chip bus clock. The paths between the slave and master interfaces of the bridge are registered to provide timing isolation. Registering the AHB signals means that accesses through the bridge incur delays.

The asynchronous bridge mode allows the on-chip and off-chip AHB bus clocks to run at completely independent frequencies. The bridge is provided with two clocks. The maximum frequency of each bus clock is only restricted by the timing for that bus. The paths between the slave and master interfaces of the bridge are registered in both clock domains to provide timing isolation. The registering of the AHB signal paths in both clock domains mean that the bridge will add several clock cycles delay to transactions.The pass-through bridge mode requires that the on-chip and off-chip AHB bus clocks to run at the same frequency. The bridge is only provided with the on-chip bus clock. The maximum frequency of the on-chip AHB bus clock is limited by the timing of signal paths off and on the chip. The paths between the slave and master interfaces of the bridge are combinatorial. As there are no registers in the AHB signal paths, the bridge will not add any delay to a transaction. This mode is designed for cycle accurate modeling of off-chip masters accessing on-chip slaves.

The block diagrams for the on-chip bus interface is shown in Figure 3.4.

Figure 3.4. AHB S interface

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