3.2.1. TCM

The ARM926PXP development chip contains 32KB of data Tightly Coupled Memory (TCM) and 32KB of instruction TCM.


Both TCMs operate with one wait state. The TCMs do not support DMA.

The caches, TCMs, Memory Management Unit (MMU), and most other system options are controlled using CP15 registers. You can only access CP15 registers with MRC and MCR instructions in a privileged mode. CDP, LDC, STC, MCRR, and MRRC instructions, and unprivileged MRC or MCR instructions to CP15 cause the UNDEFINED instruction exception to be taken.

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