ARM926EJ-S Development Chip Reference Manual 3.2.4. Bridge remapping

3.2.4. Bridge remapping

The default decoding is to have the AHB M1 selected for accesses between 0x80000000–0xFFFFFFFF and AHB M2 selected for accesses below 0x80000000 that are not decoded by a peripheral in the ARM926PXP development chip. See Figure 3.8.

Figure 3.8. AHB M1 access determined by address range

If CFGBRIDGEMEMMAP is LOW, however, the address decoding for the AHB M1 and AHB M2 buses changes as shown in Figure 3.9. The ARM D master always accesses the AHB M1 bus for regions not decoded by a peripheral in the ARM926PXP development chip and all other buses access ARM M2 for regions not decoded by a peripheral in the ARM926PXP development chip.

Figure 3.9. AHB M1 access determined by ARM D

Caution

If CFGBRIDGEMEMMAP is LOW, the ARM D and ARM I buses access different bridges for memory accesses below 0x80000000. This affects boot memory aliasing (see AHB memory alias for low memory). You must modify applications to reflect the different memory decoding.

Figure 3.10 shows the normal decoding.

Figure 3.10. Default AHB memory map with no bridge remap and SMC

The memory map for bridge remapping is shown in Figure 3.11.

Figure 3.11. AHB memory map with bridge remap and SMC

If the SSMC is not used, part of the static memory range is mapped to an external bridge. The memory map for control signals CFGBRIDGEMEMMAP LOW and MPMCnSMC HIGH is shown in Figure 3.12.

Figure 3.12. AHB memory map with bridge remap and no SMC

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