4.3.21.  CtGxiWr

The MBX GXI performs a write transfer in the same cycle as the address cycle, which is acknowledged by the GAREADY signal. The MBX initiates a write transfer request by driving GWRITE and GTRANS HIGH.

This register contains the total count of completed write transfers that have occurred on the MBX GXI Bus. The count is disabled by default. It can be controlled through AHBMONCtrlReg and reset through AHBMONRstCtrs.

Copyright © 2004, 2006 ARM Limited. All rights reserved.ARM DDI 0287B