4.3.23.  CtGxiWrAddrWait

The MBX GXI performs a write transfer in the same cycle as the address cycle, which can be stalled by taking the GAREADY signal LOW. The MBX initiates a write transfer request by driving GWRITE and GTRANS HIGH.

This register contains the total count of stalled write transfers that have occurred on the MBX GXI bus. The count is disabled by default and can be controlled through the AHBMONCtrlReg, and reset through the AHBMONRstCtrs.

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