ARM926EJ-S Development Chip Reference Manual


Table of Contents

Preface
About this document
Intended audience
Organization
Typographical conventions
Further reading
Feedback
Feedback on this document
Feedback on the ARM926PXP development chip
1. Introduction and Configuration
1. Introduction
1.1. About the ARM926PXP development chip
1.2. Functional description
1.3. External interfaces
1.3.1. External memory support
1.3.2. DMA support
2. System Controller and Configuration Logic
2.1. About the System Controller
2.1.1. Reset control
2.1.2. Interrupt response mode
2.1.3. Wait for interrupt control
2.1.4. Low battery handling
2.1.5. System controller registers
2.1.6. Watchdog and Timer module clock enable generation
2.1.7. PLL frequency control
2.1.8. System mode control
2.2. Clock control
2.2.1. Overview
2.2.2. SDRAM interaction with frequency and power modes
2.2.3. Peripheral clock selection
2.3. External configuration signals
2.4. JTAG logic
2.5. Implementation details for the ARM926EJ-S and system controller
2.6. Control, configuration, and test signals on pads
3. Memory Map and Memory Configuration
3.1. Overview of the AMBA buses in the ARM926PXP development chip
3.1.1. About the bus architecture
3.1.2. Bus matrix
3.1.3. AHB restrictions
3.1.4. AHB bus interfaces
3.1.5. Endianness
3.2. Memory map options
3.2.1. TCM
3.2.2. Memory map for internal buses
3.2.3. Selection between MPMC and SSMC as static memory controller
3.2.4. Bridge remapping
3.2.5. AHB memory alias for low memory
3.2.6. APB address maps
3.2.7. MBX memory map
3.3. AHB signals to pads
2. Controllers and Peripherals
4. AHB Monitor
4.1. About the AHB monitor
4.2. Functional description
4.2.1. Bus Cycle Analyzer
4.2.2. Profiling Counters
4.3. AHB Monitor registers
4.3.1. Ct<layer>Rd
4.3.2. Ct<layer>Wr
4.3.3. Ct<layer>Rd<x>
4.3.4. Ct<layer>Wr<x>
4.3.5. Ct<layer>BurstSingle
4.3.6. Ct<layer>BurstIncr
4.3.7. CtExpBurstWrap4
4.3.8. Ct<layer>BurstIncr4
4.3.9. CtExpBurstWrap8
4.3.10. Ct<layer>BurstIncr8
4.3.11. CtExpBurstWrap16
4.3.12. Ct<layer>BurstIncr16
4.3.13. CtArm<layer>LineFill
4.3.14. CtArmdCastOut<x>
4.3.15. CtArmdPageWalk<x>
4.3.16. Ct<layer>WaitTotal
4.3.17. Ct<layer>WaitNonSeqSlave
4.3.18. Ct<layer>WaitNonSeqBus
4.3.19. Ct<layer>WaitThresholdHit register
4.3.20. <layer>WaitThreshold register
4.3.21. CtGxiWr
4.3.22. CtGxiRd
4.3.23. CtGxiWrAddrWait
4.3.24. CtGxiRd<layer>Wait
4.3.25. CtGxiPageChange
4.3.26. GxiPageSize
4.3.27. AHBMONRstCtrs
4.3.28. AHBMONPrstCtrs
4.3.29. AHBMONCtrlReg
4.3.30. CtTotalCycles
4.3.31. CtTotalCyclesEn
4.3.32. CtTotalCyclesNonDebug
4.3.33. AHBMONPeriphID 0 to 3
4.3.34. AHBMONPCellID
4.4. AHB Monitor signals on pads
5. Color LCD Controller (CLCDC)
5.1. About the CLCDC
5.1.1. Hardware cursor support
5.2. Functional description
5.2.1. Registers
5.3. Hardware cursor extension to PL110
5.3.1. Hardware cursor extension
5.3.2. Hardware cursor registers
5.4. CLCD signals on pads
6. MOVE Coprocessor
6.1. About the MOVE Coprocessor
7. MBX HR-S Graphics Accelerator
7.1. About the ARM MBX HR-S
7.1.1. Features of the ARM MBX HR-S
7.1.2. Functional overview
7.2. Memory map and registers
7.2.1. MBX HR-S registers
7.2.2. AHB slave interface
7.2.3. GX port memory interface
8. Direct Memory Access Controller (DMAC)
8.1. About the Direct Memory Access Controller (PL080)
8.1.1. Features of the PrimeCell DMAC
8.2. Functional description
8.2.1. Peripheral integration
8.2.2. Registers
8.3. DMA signals on pads
9. General Purpose Input Output (GPIO)
9.1. About the ARM PrimeCell GPIO (PL061)
9.1.1. Features of the PrimeCell GPIO
9.2. Functional description
9.2.1. Registers
9.2.2. Implementation details
9.3. GPIO signals on pads
10. Multi-Port Memory Controller (MPMC)
10.1. About the ARM PrimeCell MPMC (GX175)
10.1.1. Features of the PrimeCell MPMC
10.1.2. Supported dynamic memory devices
10.1.3. Supported static memory devices
10.2. Functional description
10.2.1. Implementation details
10.3. MPMC signals on pads
11. Real-Time Clock (RTC)
11.1. About the Real Time Clock
11.2. Functional description
11.2.1. Registers
11.2.2. Interrupts
12. Smart Card Interface (SCI)
12.1. About the ARM SCI
12.1.1. Programmable parameters
12.2. Functional description
12.2.1. Registers
12.2.2. DMA
12.2.3. Interrupts
12.3. SCI signals on pads
13. Synchronous Static Memory Controller (SSMC)
13.1. About the ARM PrimeCell SSMC (PL093)
13.1.1. Features of the PrimeCell SSMC
13.1.2. Programmable parameters
13.1.3. Supported memory devices
13.2. Functional description
13.2.1. Implementation details
13.3. SSMC signals on pads
14. Synchronous Serial Port (SSP)
14.1. About the ARM PrimeCell SSP (PL022)
14.1.1. Features of the PrimeCell SSP
14.2. Functional description
14.2.1. Using an external reference clock
14.2.2. Registers
14.2.3. Interrupts
14.2.4. DMA
14.3. SSP signals on pads
15. Dual Timer/Counters
15.1. About the ARM Dual-Timer module (SP804)
15.1.1. Features
15.2. Functional description
15.2.1. Interrupts
15.2.2. Programmable parameters
15.2.3. Registers
16. UART Controller
16.1. About the ARM PrimeCell UART (PL011)
16.1.1. Features of the PrimeCell UART
16.2. Functional description
16.2.1. Clock signals
16.2.2. Registers
16.2.3. Interrupts
16.2.4. DMA
16.2.5. Implementation details
16.3. UART signals on pads
17. Vectored Interrupt Controller (VIC)
17.1. About the ARM PrimeCell Vectored Interrupt Controller (PL190)
17.1.1. Features of the PrimeCell VIC
17.2. Functional description
17.2.1. Interrupt request logic
17.2.2. Nonvectored FIQ interrupt logic
17.2.3. Nonvectored IRQ interrupt logic
17.2.4. Vectored interrupt block
17.2.5. Interrupt priority logic
17.2.6. Vectored interrupts
17.2.7. Software interrupts
17.2.8. Interrupt control registers
17.2.9. Implementation details
17.3. VIC signals on pads
18. ARM Vector Floating Point Coprocessor (VFP9)
18.1. About the VFP9-S coprocessor
18.2. ARMv5TE coprocessor extensions
18.3. VFP9-S system control and status registers
18.4. Modes of operation
18.4.1. Full-compliance mode
18.4.2. Flush-to-Zero mode
18.4.3. Default NaN mode
18.4.4. RunFast Mode
19. Watchdog Timer
19.1. About the Watchdog module (SP805)
19.1.1. Features
19.2. Functional description
19.2.1. Programmable parameters
19.2.2. Watchdog registers
A. Signals on Pads
A.1. Pad signals by function
B. Mechanical and Electrical Specifications
B.1. Mechanical details
B.2. Electrical specification
B.2.1. Bus interface characteristics
B.2.2. Power estimation
B.2.3. Power sequencing
C. Timing Specification
C.1. About the timing parameters
C.2. AHB bus timing
C.3. Memory timing
C.4. Peripheral timing

List of Figures

1.1. Typical application
1.2. ARM926PXP development chip block diagram
1.3. Default system bus memory map for ARM DATA AHB bus
2.1. Enable signal generation for the Timer and Watchdog modules
2.2. Reference frequency select for Watchdog and Timer modules clock enable
2.3. System mode control state machine
2.4. Clock and reset block diagram
2.5. External clock signals and clock selection
2.6. Power-on configuration block diagram
2.7. JTAG Test Access Port
2.8. Multi-ICE synchronization
3.1. Bus matrix configuration
3.2. AHB M1 interface
3.3. AHB M2 interface
3.4. AHB S interface
3.5. Memory control signals
3.6. Default AHB memory map with SMC
3.7. AHB memory map without SMC
3.8. AHB M1 access determined by address range
3.9. AHB M1 access determined by ARM D
3.10. Default AHB memory map with no bridge remap and SMC
3.11. AHB memory map with bridge remap and SMC
3.12. AHB memory map with bridge remap and no SMC
3.13. Supported address remap functionality for ARM D AHB
3.14. Alias for REMAPSTATIC LOW
3.15. Alias for REMAPSTATIC HIGH and MPMCnSMC LOW
3.16. Alias for REMAPSTATIC HIGH and MPMCnSMC HIGH
3.17. Alias for REMAPEXTERNAL HIGH and CFGBRIDGEMEMMAP HIGH
3.18. Alias for REMAPEXTERNAL HIGH and CFGBRIDGEMEMMAP LOW
3.19. APB map
3.20. MBX map
4.1. AHB monitor block diagram
4.2. AHB Monitor packet format
4.3. Peripheral ID register
4.4. PrimeCell ID register
5.1. CLCDC internal organization
5.2. CLCDC block diagram
5.3. Hardware cursor block diagram
5.4. Hardware cursor movement
5.5. Hardware cursor clipping
5.6. Hardware cursor image format
5.7. ClcdCrsrCtrl Register bit assignments
5.8. ClcdCrsrConfig Register bit assignments
5.9. ClcdCrsrPalette0 and ClcdCrsrPalette1 Register bit assignments
5.10. ClcdCrsrXY Register bit assignments
5.11. ClcdCrsrClip Register bit assignments
5.12. ClcdCrsrIMSC Register bit assignments
5.13. ClcdCrsrICR Register bit assignments
5.14. ClcdCrsrRIS Register bit assignments
5.15. ClcdCrsrMIS Register bit assignments
5.16. CLCDPeriphID0-3 Register bit assignments
5.17. CLCDCPCellID0-3 Register bit assignments
6.1. MOVE overview
7.1. ARM MBX HR-S top level block diagram
7.2. MMU address translation
8.1. DMAC interface block diagram
9.1. GPIO output control
10.1. MPMC PrimeCell block diagram
11.1. PrimeCell RTC
12.1. SCI block diagram
13.1. SSMC interface block diagram
13.2. Address and control multiplexor
13.3. Data multiplexor
14.1. PrimeCell SSP block diagram
15.1. Simplified block diagram
16.1. PrimeCell UART block diagram
17.1. VIC block diagram
17.2. Interrupt request logic
17.3. Nonvectored FIQ interrupt logic
17.4. Nonvectored IRQ interrupt logic
17.5. Vectored interrupt block
17.6. Interrupt priority logic
19.1. Simplified block diagram
B.1. BGA numbering, ball side view
C.1. AC timing example

List of Tables

1.1. MPMC port allocation
2.1. System mode control signal states
2.2. External peripheral clocks and clock control signals
2.3. Configuration signal sources
2.4. Configuration signal destinations
2.5. ARM926EJ-S signals
2.6. ETM signals
2.7. Reset and configuration signals
2.8. Clock signals
2.9. JTAG TAP signals
3.1. On-chip bridge selection
3.2. DMA APB peripheral base addresses
3.3. Core APB peripheral base addresses
3.4. AHB M1 signals
3.5. AHB M2 signals
3.6. AHB S signals
4.1. Cycle states
4.2. Sample output
4.3. Bus state bit patterns
4.4. Bit patterns for GXI states for read channel
4.5. Bit patterns for GXI state for address channel
4.6. Event counters for the ARM-I layer
4.7. CLCDC events
4.8. DMA 0 events
4.9. DMA 1 events
4.10. EXP layer events
4.11. D layer events
4.12. GXI events
4.13. Other events
4.14. AHB Monitor registers
4.15. <layer>WaitThreshold
4.16. GxiPageSize
4.17. AHBMONCtrlReg
4.18. AHBMONPeriphID
4.19. Output pad signal descriptions
5.1. PrimeCell CLCDC register differences
5.2. Supported cursor images
5.3. 32x32 cursor base addresses
5.4. LBBP buffer to pixel mapping 32x32 Cursor0 for datawords [31:16]
5.5. LBBP buffer to pixel mapping 32x32 Cursor0 for datawords [15:0]
5.6. LBBP buffer to pixel mapping 64x64 for datawords [31:16]
5.7. LBBP buffer to pixel mapping 64x64 for datawords [15:0]
5.8. 32x32 software mask storage
5.9. 64x64 software mask storage
5.10. Pixel encoding
5.11. PrimeCell CLCDC register summary
5.12. ClcdCrsrCtrl Register bit assignments
5.13. ClcdCrsrConfig Register bit assignments
5.14. ClcdCrsrPalette0 and ClcdCrsrPalette1 Register bit assignments
5.15. ClcdCrsrXY Register bit assignments
5.16. ClcdCrsrClip Register bit assignments
5.17. ClcdCrsrIMSC Register bit assignments
5.18. ClcdCrsrICR Register bit assignments
5.19. ClcdCrsrRIS Register bit assignments
5.20. ClcdCrsrMIS Register bit assignments
5.21. Peripheral Identification Register options
5.22. CLCDPeriphID0 Register bit assignments
5.23. CLCDPeriphID1 Register bit assignments
5.24. CLCDPeriphID2 Register bit assignments
5.25. CLCDPeriphID3 Register bit assignments
5.26. CLCDPCellID0 Register bit assignments
5.27. CLCDPCellID1 Register bit assignments
5.28. CLCDPCellID2 Register bit assignments
5.29. CLCDPCellID3 Register bit assignments
5.30. External pad output signals
7.1. MBX HR-S memory map
8.1. DMA channel allocation
8.2. DMA request and response signal descriptions
9.1. On-chip signal descriptions
9.2. Pad signal descriptions
10.1. Pad interface and control signal descriptions
12.1. Interrupts
12.2. SCI signals
13.1. Internal signal descriptions
13.2. Pad signals
14.1. Pad signal descriptions
16.1. Pad signal descriptions
17.1. Tied off or unused signals
17.2. Interrupt controller pad signals
18.1. Access to control registers
A.1. Pad signals
B.1. Interface signal electrical characteristics
B.2. Operating ranges
B.3. Power estimate
C.1. ARM926PXP development chip bus timing
C.2. ARM926PXP development chip memory timing
C.3. Peripherals and controller timing

Proprietary Notice

Words and logos marked with® or ™ are registered trademarks or trademarks of ARM Limited in the EU and other countries, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners.

Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.

The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM Limited in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developed product.

Conformance Notices

This section contains conformance notices.

Federal Communications Commission Notice

This device is test equipment and consequently is exempt from part 15 of the FCC Rules under section 15.103 (c).

CE Declaration of Conformity

A system using this development chip should be powered down when not in use.

The ARM926PXP development chip generates, uses, and can radiate radio frequency energy and may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If equipment using the ARM926PXP development chip causes harmful interference to radio or television reception, which can be determined by turning the equipment off or on, you are encouraged to try to correct the interference by one or more of the following measures:

  • ensure attached cables do not lie across the card

  • reorient the receiving antenna

  • increase the distance between the equipment and the receiver

  • connect the equipment into an outlet on a circuit different from that to which the receiver is connected

  • consult the dealer or an experienced radio/TV technician for help

Note

It is recommended that wherever possible shielded interface cables be used.

Revision History
Revision AApril 2004New document
Revision BAugust 2006Second release, updated to fix defects on AHB monitor and AHB bus graphics.
Copyright © 2004, 2006 ARM Limited. All rights reserved.ARM DDI 0287B
Non-Confidential