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An alignment fault occurs if the ARM1156T2F-S processor has attempted to access a particular data memory size at an address location that is not aligned with that size.
For details on conditions for generating Alignment faults, see the ARM Architecture Reference Manual.
Alignment checks are performed with the MPU both enabled and disabled.
The alignment fault for doubleword load and store (LDRD, STRD)
is strengthened:
When U is set to 0 to trap if not aligned to an even word address. That is,
address bits [2:0] != 0.
When U is set to 1 to trap if not aligned to a word boundary, That is, address bits [1:0] != 0.
| Copyright © 2005-2007 ARM Limited. All rights reserved. | ARM DDI 0290G |
| Non-Confidential | |
| PDF version | |
| Home > Memory Protection Unit > MPU fault checking > Alignment fault |