| Copyright © 2005-2007 ARM Limited. All rights reserved. | ARM DDI 0290G |
| Non-Confidential | |
 PDF version | |
| Home > System Control Coprocessor > System control processor registers > c1, Control Register |
| |||
| Home > System Control Coprocessor > System control processor registers > c1, Control Register | |||
The purpose of the Control Register is to provide control and configuration of:
memory alignment, endianness, protection, and fault behavior
MPU and cache enables and cache replacement strategy
interrupts and the behavior of interrupt latency
the location for exception vectors
program flow prediction.
You can use the Control Register to enable and disable system configuration options.
The Control Register is:
in CP15 c1
a 32-bit register
accessible in privileged modes only.
Figure 3.27 shows the arrangement of bits in the register.
Table 3.24 shows how the bit values correspond with the Control Register controls.
Table 3.24. Control Register bit functions
Bits | Field | Function |
|---|---|---|
[31] | SBZ | This field returns a Unpredictable value when read. Should Be Zero. |
| [30] | TE | Determines the state that the processor enters exceptions: 0 = Exceptions entered in ARM state 1 = Exceptions entered in Thumb state. |
| [29] | SBZ | Should Be Zero. This bit reads as 0 and ignores writes. |
| [28] | SBZ | Should Be Zero. This bit reads as 0 and ignores writes. |
| [27] | NMI | Determines the state of the non-maskable bit that is set by a configuration pin FIQISNMI: 0 = The processor is backwards compatible and behaves as normal 1 = All attempts to modify the CPSR F bit can only clear it. There is no way to set it in software. The SPSRs remain freely modifiable but copying the SPSR to CPSR can only clear the F bit. FIQs continue to set the F bit automatically. NoteThe status of the FIQISNMI pin is read by Bit 27. Software cannot write to Bit 27. |
| [26] | SBZ | Should Be Zero. This bit reads as 0 and ignores writes. |
| [25] | EE | Determines how the E bit in the CPSR bit is set on an exception: 0 = CPSR E bit is set to 0 on an exception 1 = CPSR E bit is set to 1 on an exception. The reset value depends on external signals, see Table 3.25. |
| [24] | VE | Enables the VIC interface to determine interrupt vectors: 0 = Interrupt vectors are fixed 1 = Interrupt vectors are defined by the VIC interface. See the description of the V bit, bit 13. |
| [23] | SBZ | Should Be Zero. This bit reads as 0 and ignores writes. |
| [22] | U | Enables unaligned data access operations for mixed little-endian and big-endian operation: 0 = Unaligned data access support disabled 1 = Unaligned data access support enabled. The A bit has priority over the U bit. The reset value of the U bit depends on external signals, see Table 3.25. |
| [21] | FI | Configures low latency features for fast interrupts. 0 = All performance features enabled. 1 = Low interrupt latency configuration enabled. |
| [20] | SBZ | Should Be Zero. This bit reads as 0 and ignores writes. |
| [19] | SBZ | Should Be Zero. This bit reads as 0 and ignores writes. |
| [18] | SBO | Should Be One. This bit reads as 1 and ignore writes. |
| [17] | SBZ | Should Be Zero. This bit reads as 0 and ignores writes. |
| [16] | SBO | Should Be One. This bit reads as 1 and ignore writes. |
[15] | L4 | Determines if the T bit is set for PC load instructions: 0 = Loads to PC set the T bit. 1 = Loads to PC do not set the T bit, ARMv4 behavior. For more details, see the ARM Architecture Reference Manual. |
[14] | RR | Determines the replacement strategy for the cache: 0 = Normal replacement strategy by random replacement 1 = Predictable replacement strategy by round-robin replacement. |
| [13] | V | Determines the location of exception vectors: 0 = Normal exception vectors selected, address
range = 1 =
High exception vectors selected, address range = |
| [12] | I | Enable or disable level one instruction cache: 0 = disabled 1 = enabled. |
| [11] | Z | Enables programme flow prediction: 0 = Program flow prediction disabled 1 = Program flow prediction enabled. |
| [10:8] | SBZ | Should Be Zero. This bit reads as 0 and ignores writes. |
| [7] | B | Determines operation as little-endian or big-endian memory system and the names of the low four-byte addresses within a 32-bit word: 0 = Little-endian memory system 1 = Big-endian word-invariant memory system. The reset value of the B bit depends on external signals, see Table 3.25. |
| [6:3] | SBO | Should Be One. This field read as 1 and ignore writes. |
| [2] | C | Enables or disables level one data cache: 0 = Data cache disabled 1 = Data cache enabled. |
| [1] | A | Enables strict alignment of data to detect alignment faults in data accesses: 0 = Strict alignment fault checking disabled. 1 = Strict alignment fault checking enabled. The A bit setting takes priority over the U bit. |
| [0] | M | Enables or disables the MPU: 0 = MPU disabled 1 = MPU enabled. |
Normally, to set the V bit and the B, EE, and U bits you configure signals at reset.
The V bit depends on VINITHI at reset:
VINITHI LOW sets V to 0
VINITHI HIGH sets V to 1.
The B, EE, and U bits depend on how you set BIGENDINIT and UBITINIT at reset. CFGBIGEND makes these signals available.
Table 3.25 shows the values of the B, EE, and U bits that result for the reset values of these signals.
Table 3.25. Resultant B bit, U bit, and EE bit values
| CFGBIGEND at reset | EE | U | B | |
|---|---|---|---|---|
| UBITINIT | BIGENDINIT | |||
| 0 | 0 | 0 | 0 | 0 |
| 0 | 1 | 0 | 0 | 1 |
| 1 | 0 | 0 | 1 | 0 |
| 1 | 1 | 1 | 1 | 0 |
These bits in the Control Register exhibit specific behavior:
The A bit setting takes priority over the U bit. The Data Abort trap is taken if strict alignment is enabled and the data access is not aligned to the width of the accessed data item.
Use of this bit is deprecated in the ARM1156T2F-S processor.
In ARMv6, the TCM blocks have individual enables that apply to each block. As a result, this bit is now redundant and Should Be One. See c9, Data TCM Region Register for a description of the ARM1156T2F-S TCM enables.
Use of this bit is deprecated in the ARM1156T2F-S processor.
In ARMv6, the TCM blocks have individual enables that apply to each block. As a result, this bit is now redundant and Should Be One. See c9, Instruction TCM Region Register for a description of the ARM1156T2F-S TCM enables.
This bit is not used in the ARM1156T2F-S processor.
This bit is not used in the ARM1156T2F-S processor.
The ARM1156T2F-S processor does not implement the write buffer enable because all memory writes take place through the Write Buffer.
To use the Control Register it is recommended that you use a read modify write technique. To use the Control Register read or write CP15 with:
Opcode_1 set to 0
CRn set to c1
CRm set to c0
Opcode_2 set to 0.
For example:
MRC p15, 0, <Rd>, c1, c0, 0 ;Read Control Register configuration data
MCR p15, 0, <Rd>, c1, c0, 0 ;Write Control Register configuration data
| Copyright © 2005-2007 ARM Limited. All rights reserved. | ARM DDI 0290G |
| Non-Confidential | |
| PDF version | |
| Home > System Control Coprocessor > System control processor registers > c1, Control Register |