ARM1156T2F-S™ Technical Reference Manual 3.2.10. c1, Auxiliary Control Register

3.2.10. c1, Auxiliary Control Register

The purpose of the Auxiliary Control Register is to control:

program flow
fast interrupt control
cache cleaning.

For more information on how the system control coprocessor operates with caches, see Cache configuration and control.

The Auxiliary Control Register is:

in CP15 c1
a 32-bit read/write register
accessible in privileged modes only.

Figure 3.28 shows the bit arrangement of the Auxiliary Control Register.

Figure 3.28. Auxiliary Control Register format

Table 3.26 shows how the bit values correspond with the Auxiliary Control Register functions.

Table 3.26. Auxiliary Control Register bit functions

Bits	Field	Function
[31:10]	-	Should Be Zero on writes, Unpredictable on reads. Reserved.
[9]	NS	Override Shared attribute in Normal, Noncacheable data regions when the MPU is disabled or not present: 0 = Shared, Normal, Noncacheable 1 = Not Shared, Normal, Noncacheable.
[8]	BC^[1]	Enables or disables the dynamic branch pattern cache, if program flow prediction is enabled by Z bit, bit 11, of CP15 Register c1^[2]: 0 = Dynamic branch predictor pattern cache disabled 1 = Dynamic branch predictor pattern cache enabled.
[7]	BL^a	Enables or disables the dynamic branch predictor loop cache, if program flow prediction is enabled by Z bit, bit 11, of CP15 Register c1^b: 0 = Dynamic branch predictor loop cache: disabled 1 = Dynamic branch predictor loop cache enabled.
[6]	IR	Enables or disables instruction cache reload on a parity error if PE, bit 2, is set: 0 = Instruction cache reload on a parity error disabled 1 = Instruction cache reload on a parity error enabled.
[5]	RV	Enables or disables block transfer cache operations: 0 = Block transfer cache operations enabled 1 = Block transfer cache operations disabled.
[4]	RA	Enables or disables clean entire data cache: 0 = Clean entire data cache enabled 1 = Clean entire data cache disabled.
[3]	FE	Enables or disables branch folding within the prefetch unit, if program flow prediction is enabled by Z bit, bit 11, of CP15 Register c1^b: 0 = Branch Folding is disabled 1 = Branch Folding is enabled.
[2]	PE	Enables or disables the generation and checking of parity information for the Instruction and Data caches, and the Instruction and Data TCMs: 0 = Parity generation disabled. When disabled the processor writes 0 (zero) to parity bits of the RAM. Parity errors ignored by the processor. 1 = Parity generation enabled. When enabled Odd parity are written to parity bits of the RAM. Parity errors reported to processor.
[1]	DB	Enables or disables the use of the Dynamic Predictor, if program flow prediction is enabled by Z bit, bit 11, of CP15 Register^b: 0 = Dynamic Prediction is disabled 1 = Dynamic Prediction is enabled.
[0]	RS^a	Enables or disables the use of the return stack if program flow prediction is enabled. by Z bit, bit 11, of CP15 Register c1^{^b} 0 = Return stack is disabled 1 = Return stack is enabled.
^[1]The BC, BL, and RS bits are set on reset ^[2]For more details, see Enabling/disabling program flow prediction.

To use the Auxiliary Control Register you must use a read modify write technique.

To access the Auxiliary Control Register read or write CP15 with:

Opcode_1 set to 0
CRn set to c1
CRm set to c0
Opcode_2 set to 1.

For example:

MRC p15, 0, <Rd>, c1, c0, 1 ;Read Auxiliary Control Register

MCR p15, 0, <Rd>, c1, c0, 1 ;Write Auxiliary Control Register

ARM Limited recommends that you use a read modify write technique.

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