ARM1156T2F-S™ Technical Reference Manual 1.3.8. Vector Floating-Point (VFP)

1.3.8. Vector Floating-Point (VFP)

The VFP coprocessor supports floating point arithmetic operations and is a functional block within the ARM1156T2F-S processor. The VFP coprocessor is mapped as coprocessor numbers 10 and 11. Software can determine whether the VFP is present by the use of the Coprocessor Access Control Register. For more details, see c1, Coprocessor Access Control Register.

Note

The ARM1156T2-S processor does not include a VFP coprocessor.

For more details, see Chapter 19 VFP Introduction to Chapter 23 VFP Exception Handling.

IEEE754 compliance

The VFP supports all five floating point exceptions defined by IEEE754:

invalid operation
divide by zero
overflow
underflow
inexact.

You can individually enable or disable these exception traps. If disabled, the IEEE754-defined default results are returned. All rounding modes are supported, and basic single and basic double formats are used.

For full compliance, the VFP requires support code to handle arithmetic where operands or results are de-norms. This support code is normally installed on the Undefined instruction exception handler. For more information see IEEE Standard for Binary Floating-Point Arithmetic.

Flush-to-zero mode

A flush-to-zero mode is provided where a default treatment of de-norms is applied. Table 1.1 shows the default behavior in flush-to-zero mode.

Table 1.1. Flush-to-zero mode

Operation	Flush-to-zero
De-norm operand(s)	Treated as 0+n Inexact flag set
De-norm result	Returned as 0+n Inexact Flag set

Operations not supported

The following operations are not directly supported by the VFP:

remainder
binary (decimal) conversions
direct comparisons between single and double-precision values.

These are normally implemented as C library functions.

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