In ARMv5, the IRQ and FIQ exception vectors are fixed. Interrupt handlers typically have to start with an instruction sequence to determine the cause of the interrupt and branch to a routine to handle it.

On the ARM1156T2F-S processor the IRQ exception can be determined directly from the value presented on the Vectored Interrupt Controller (VIC) port. The vector interrupt behavior is explicitly enabled when the VE bit in CP15 c1 is set. See Chapter 12 Vectored Interrupt Controller Port.

An example of a hardware block that can interface to the VIC port is the PrimeCell VIC (PL192), which is available from ARM Limited. This takes a set of inputs from various interrupt sources, prioritizes them, and presents the interrupt type of the highest-priority interrupt being requested and the address of its handler to the processor core. The VIC also masks any lower priority interrupts. Such hardware reduces the time taken to enter the handling routine for the required interrupt.