The reset signals present in the ARM1156T2F-S processor design
to enable you to reset different parts of the design independently.
The reset signals, and the combinations and possible applications
that you can use them in, are shown in Table 9.1.
Table 9.1. Reset modes
| Reset mode | nRESETIN | DBGnTRST | nPORESETIN | Application |
|---|
| Power-on reset | 0 | x | 0 | Reset at power up, full system reset. Hard
reset or cold reset. |
| Processor reset | 0 | x | 1 | Reset of processor core only, watchdog reset.
Soft reset or warm reset. |
| DBGTAP reset | 1 | 0 | 1 | Reset of DBGTAP logic. |
| Normal | 1 | x | 1 | Normal run mode. |
Note
If nRESETIN is set to 1
and nPORESETIN is set to 0 the
behavior is architecturally Unpredictable.
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