22.7.1. Status register RAW hazard example
In Example 22.4, the
FMSTAT is stalled for four cycles in the Decode stage until the FCMPS
updates the condition codes in the FPSCR register. Two cycles later,
the FMSTAT writes the condition codes to the ARM11 processor.
Example 22.4. FCMPS-FMSTAT RAW hazard
FCMPS S1, S2
FMSTAT
Table 22.6 shows
the VFP11 pipeline stages for Example 22.4.
Table 22.6. FCMPS-FMSTAT RAW hazard
| | Instruction cycle number |
|---|
| Instruction | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 |
|---|
| FCMPS | D | I | E1 | E2 | E3 | E4 | - | - | - | - | - |
| FMSTAT | - | D | D | D | D | D | I | E | M1 | M2 | W |
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