You must apply power-on or cold reset to the ARM1156T2F-S processor when power is first applied to the system. In the case of power-on reset, the leading (falling) edge of the reset signals, nRESETIN and nPORESETIN, does not have to be synchronous to CLKIN. Because the nRESETIN and nPORESETIN signals are synchronized within the ARM1156T2F-S processor, you do not have to synchronize these signals. Figure 9.1 shows the application of power-on reset.

It is recommended that you assert the reset signals for at least three CLKIN cycles to ensure correct reset behavior. Adopting a three-cycle reset eases the integration of other ARM parts into the system, for example, ARM9TDMI-based designs.

It is not necessary to assert DBGnTRST on power-up.