The ARM11/VFP11 interface specifies that an exceptional instruction that bounces to support code must signal on a subsequent coprocessor instruction. This is known as imprecise exception handling. It means that when the exception is processed, the VFP11 and ARM11 user states might be different from their states when the exceptional instruction executed. Parallel execution of VFP11 CDP instructions and data transfer instructions enables the VFP11 and ARM11 register files and memory to be modified outside of the program order.