ARM1156T2F-S™ Technical Reference ManualRevision: r0p4
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2.8.4. Entering an exception

When handling an exception the ARM1156T2F-S processor:

  1. Preserves the address of the next instruction in the appropriate LR. When the exception entry is from:

    ARM state:

    The ARM1156T2F-S processor writes the value of the PC into the LR, offset by a value (current PC + 4 or PC + 8 depending on the exception) that causes the program to resume from the correct place on return

    Thumb state:

    The ARM1156T2F-S processor writes the value of the PC into the LR, offset by a value (current PC + 2, PC + 4 or PC + 8 depending on the exception) that causes the program to resume from the correct place on return.

  2. Copies the CPSR into the appropriate SPSR. Depending on the exception type, the processor might modify the IT execution state bits of the CPSR prior to this operation to facilitate a return from the exception.

  3. Forces the CPSR mode bits to a value that depends on the exception and clears the IT execution state bits in the CPSR.

  4. Forces the PC to fetch the next instruction from the relevant exception vector.

The ARM1156T2F-S processor can also set the interrupt disable flags to prevent otherwise unmanageable nesting of exceptions.

ARM state or Thumb state can enter, handle, and exit exceptions. At reset the TEINIT pin controls the state used to manage exceptions.

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