ARM1156T2F-S™ Technical Reference Manual 2.8. Exceptions

2.8. Exceptions

Exceptions occur whenever the normal flow of a program has to be halted temporarily. For example, to service an interrupt from a peripheral. Before attempting to handle an exception, the ARM1156T2F-S processor preserves the current processor state so that the original program can resume when the handler routine has finished.

Exception priorities describes how the exceptions are dealt with in the fixed order if two or more exceptions occur simultaneously.

This section provides details of the ARM1156T2F-S exception handling:

Several enhancements are made in ARM architecture v6 to the exception model, mostly to improve interrupt latency, as follows:

New instructions are added to give a choice of stack to use for storing the exception return state after exception entry, and to simplify changes of processor mode and the disabling and enabling of interrupts.
The interrupt vector definitions on ARMv6 are changed to support the addition of hardware to prioritize the interrupt sources and to look up the start vector for the related interrupt handling routine.
A low interrupt latency configuration is added in ARMv6. In terms of the instruction set architecture, it specifies that multi-access load/store instructions can be interrupted and then restarted after the interrupt has been processed:
ARM
LDC, LDM, LDRD, STC, STM, and STRD,
Thumb
LDC, LDM, LDRD, STC, STM, STRD, LDM, POP, and PUSH.
Support for an imprecise Data Abort that behaves as an interrupt rather than as an abort, in that it occurs asynchronously relative to the instruction execution. Support involves the masking of a pending imprecise Data Abort at times when entry into Abort mode is deemed unrecoverable.
Exception handling in ARM or Thumb state set by the TE Bit, bit [30], CP15 register c1. For more details, see c1, Control Register.

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