Figure 7.2 shows an example of a TCM read access. The processor drives the address and control to the memory on the rising edge of the processor clock. The processor clock is inverted to produce RAM clock. This signal drives the RAM block on its rising edge. This enables the processor to have a complete clock cycle for the memory access to the RAM block.

To align the data with the processor clock, a transparent latch opens at the end of the RAM access and the data is captured on the rising edge of the processor clock two cycles after the edge which started the transfer.

Figure 7.3 shows an example of a TCM write access. The RAM control signals are generated from the rising edge of the processor clock, and are held for one processor clock cycle. The write data is asserted at the same time. TCDATABW is an eight bit bus that indicates which bytes are to be written to memory. Figure 7.32 shows that all eight bytes are written to RAM.

The processor supports parity errors for the TCMs. If parity is enabled, that is bit 2 of the Auxiliary Control register is set to 1, see c1, Auxiliary Control Register, the processor generates parity bits for each byte written to the TCM. The processor implements an odd-parity scheme. The processor generates parity bits in parallel to the write data. The parity bits timing is the same as the write data.

The parity checking logic for the TCMs is added outside of the processor. For additional information see the ARM1156T2F-S and ARM1156T2-S Integration Manual.

Figure 7.4 shows an example of a parity error generated on a read access.

Access to RAM is activated on the rising edge of the RAM clock. If parity is implemented for the TCM, the parity bits are read at the same time as the data. The parity bits are checked for each byte and a parity error is generated if the parity is incorrect. A parity error on any byte generates a data abort exception for data accesses unless the access is the result of a source misprediction. A parity error for an opcode access generates a prefetch abort exception if the access reaches the execution stage of the processor pipeline.

In systems that require fault tolerance, it is possible to implement error correction on the TCMs. Figure 7.5 shows an example where the read results in an error being detected by the external ECC logic. This error causes a stall to be inserted, nTCDATARDY. During this cycle, the ECC logic can attempt to correct the error using the error correction codes stored in the TCM. If this is successful, the error flags are cleared and the access completed by de-asserting nTCDATARDY.

If the error correction is unsuccessful, the access completes by:

Because of the pipelined nature of the TCM accesses it is possible for the processor to issue three accesses before a stall is recognized. Figure 7.6 shows an example of three read accesses.

The processor issues access A that causes nTCDATARDY to be asserted. Access B is issued before the processor can register the stall signal. Access C is issued because nTCDATARDY is registered by the processor before being used. This prevents the cancellation of access C.

The external wait generation logic must ignore accesses B and C. These accesses are re-issued in order by the processor.

Figure 7.7 shows that the processor can issue three write accesses before the stall signal is recognized.

The wait state generation logic must ignore the accesses when nTCDATARDY and a pipelined version of this signal are asserted.

Because there is a considerable delay before restarting the transactions when the processor initially registers the TCM interface outputs and the nTCDATARDY input, it is recommended that you do not use the stall mechanism as a wait state mechanism to support slow memories, with wait states for each access.

You can use the stall mechanism for infrequent events such as error correction or resolving arbitration clashes when an external DMA has access to the TCMs.