ARM1156T2F-S™ Technical Reference ManualRevision: r0p4
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8.5.17. Noncacheable LDM14

A Noncacheable LDM14 is split into two or three operations as shown in Table 8.40.

Table 8.40. Noncacheable LDM14

Address[4:0]Operations
0x00, word 0LDM8 from 0x00 + LDM6 from 0x00
0x04, word 1LDM7 from 0x04 + LDM7 from 0x00
0x08, word 2LDM6 from 0x08 + LDM8 from 0x00
0x0C, word 3LDM5 from 0x0C + LDM8 from 0x00 + LDR from 0x00
0x10, word 4LDM4 from 0x10 + LDM8 from 0x00 + LDM2 from 0x00
0x14, word 5LDM3 from 0x14 + LDM8 from 0x00 + LDM3 from 0x00
0x18, word 6LDM2 from 0x18 + LDM8 from 0x00 + LDM4 from 0x00
0x1C, word 7LDR from 0x1C + LDM8 from 0x00 + LDM5 from 0x00
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