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Table 18.1 shows AXI bus interface input port timing parameters.
Table 18.1. AXI bus interface input port timing parameters:
| Input delay Min. | Input delay Max. | Signal name |
|---|---|---|
| Clock uncertainty | 40% | ACLKENRW |
| Clock uncertainty | 50% | ARREADYRW |
| Clock uncertainty | 50% | AWREADYRW |
| Clock uncertainty | 50% | WREADYRW |
| Clock uncertainty | 50% | BVALIDRW |
| Clock uncertainty | 50% | RVALIDRW |
| Clock uncertainty | 70% | RLASTRW |
| Clock uncertainty | 70% | BRESPRW[1:0] |
| Clock uncertainty | 70% | RRESPRW[1:0] |
| Clock uncertainty | 70% | RDATARW[63:0] |
| Clock uncertainty | 40% | ACLKENI |
| Clock uncertainty | 50% | ARREADYI |
| Clock uncertainty | 50% | AWREADYI |
| Clock uncertainty | 50% | WREADYI |
| Clock uncertainty | 50% | BVALIDI |
| Clock uncertainty | 50% | RVALIDI |
| Clock uncertainty | 70% | RLASTI |
| Clock uncertainty | 70% | BRESPI[1:0] |
| Clock uncertainty | 70% | RRESPI[1:0] |
| Clock uncertainty | 70% | RDATAI[63:0] |
| Clock uncertainty | 40% | ACLKENP |
| Clock uncertainty | 50% | ARREADYP |
| Clock uncertainty | 50% | AWREADYP |
| Clock uncertainty | 50% | WREADYP |
| Clock uncertainty | 50% | BVALIDP |
| Clock uncertainty | 50% | RVALIDP |
| Clock uncertainty | 70% | BRESPP[1:0] |
| Clock uncertainty | 70% | RRESPP[1:0] |
| Clock uncertainty | 70% | RDATAP[63:0] |
Table 18.2 shows TCM interface port timing parameters.
Table 18.2. TCM interface port timing parameters
| Input delay Min. | Input delay Max. | Signal name |
|---|---|---|
| Clock uncertainty | 40% | DTCDATAOUT[63:0] |
| Clock uncertainty | 40% | DTCDATAERROR[7:0] |
| Clock uncertainty | 40% | nDTCDATARDY |
| Clock uncertainty | 40% | ITCDATAOUT[63:0] |
| Clock uncertainty | 40% | ITCDATAERROR[7:0] |
| Clock uncertainty | 40% | nITCDATARDY |
Table 18.3 shows coprocessor port timing parameters.
Table 18.3. Coprocessor port timing parameters
| Input delay Min. | Input delay Max. | Signal name |
|---|---|---|
| Clock uncertainty | 70% | CPALENGTHHOLD |
| Clock uncertainty | 70% | CPAACCEPT |
| Clock uncertainty | 70% | CPAACCEPTHOLD |
| Clock uncertainty | 70% | CPASTDATAV |
| Clock uncertainty | 70% | CPALENGTH[3:0] |
| Clock uncertainty | 70% | CPALENGTHT[3:0] |
| Clock uncertainty | 70% | CPAACCEPTT[3:0] |
| Clock uncertainty | 70% | CPASTDATA[63:0] |
| Clock uncertainty | 70% | CPASTDATAT[3:0] |
| Clock uncertainty | 70% | CPAPRESENT[11:0] |
Table 18.4 shows ETM interface port timing parameters.
Table 18.4. ETM interface port timing parameters
| Input delay Min. | Input delay Max. | Signal name |
|---|---|---|
| Clock uncertainty | 60% | ETMPWRUP |
| Clock uncertainty | 60% | nETMWFIREADY |
| Clock uncertainty | 60% | ETMEXTOUT[1:0] |
| Clock uncertainty | 60% | ETMCPRDATA[31:0] |
Table 18.5 shows interrupt port timing parameters.
Table 18.5. Interrupt port timing parameters
| Input delay Min. | Input delay Max. | Signal name |
|---|---|---|
| Clock uncertainty | 60% | nFIQ |
| Clock uncertainty | 60% | nIRQ |
| Clock uncertainty | 60% | INTSYNCEN |
| Clock uncertainty | 60% | IRQADDRV |
| Clock uncertainty | 60% | IRQADDRVSYNCEN |
| Clock uncertainty | 60% | IRQADDR[31:2] |
Table 18.6 shows debug port timing parameters.
Table 18.6. Debug port timing parameters
| Input delay Min. | Input delay Max. | Signal name |
|---|---|---|
| Clock uncertainty | 40% | DBGTCKEN |
| Clock uncertainty | 40% | FREEDBGTCKEN |
| Clock uncertainty | 50% | DBGMANID[10:0] |
| Clock uncertainty | 50% | DBGTDI |
| Clock uncertainty | 50% | DBGTMS |
| Clock uncertainty | 50% | DBGVERSION[3:0] |
| Clock uncertainty | 60% | DBGnTRST |
| Clock uncertainty | 60% | EDBGRQ |
| Clock uncertainty | 60% | DBGEN |
Table 18.7 shows test port timing parameters
Table 18.7. Test port timing parameters
| Input delay Min. | Input delay Max. | Signal name |
|---|---|---|
| Clock uncertainty | 20% | RSTBYPASS |
| Clock uncertainty | 20% | SE |
| Clock uncertainty | 20% | SI* |
| Clock uncertainty | 60% | MBISTADDR[14:0] |
| Clock uncertainty | 60% | MBISTCE[16:0] |
| Clock uncertainty | 60% | MBISTDIN[71:0] |
| Clock uncertainty | 60% | MBISTWE[7:0] |
| Clock uncertainty | 20% | MTESTON |
Table 18.8 shows static configuration signal port timing parameters
Table 18.8. Static configuration signal port timing parameters
| Input delay Min. | Input delay Max. | Signal name |
|---|---|---|
| Clock uncertainty | 60% | BIGENDINIT |
| Clock uncertainty | 60% | UBITINIT |
| Clock uncertainty | 60% | INITRAM |
| Clock uncertainty | 60% | VINITHI |
| Clock uncertainty | 60% | TEINIT |
| Clock uncertainty | 60% | FIQISNMI |
| Clock uncertainty | 60% | CFGITCMSZ[3:0] |
| Clock uncertainty | 60% | CFGDTCMSZ[3:0] |
| Copyright © 2005-2007 ARM Limited. All rights reserved. | ARM DDI 0290G |
| Non-Confidential | |
| PDF version | |
| Home > AC Characteristics > ARM1156T2F-S timing parameters > Input port timing parameters |