ARM1156T2F-S™ Technical Reference ManualRevision: r0p4
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18.2.2. Output ports timing parameters

Most output ports have a maximum output delay of 60%, that is the SoC is enabled to use 60%of the clock cycle. Table 18.9 shows output port timing parameters exceptions.

Table 18.9. Output ports timing parameters

Output delay Min.Output delay Max.Signal name
Clock uncertainty70%DTCDATAEN0
Clock uncertainty70%DTCDATAEN1
Clock uncertainty70%DTCDATAWRITE
Clock uncertainty70%DTCDATABYTEWR[7:0]
Clock uncertainty70%DTCDATAADDR[17:3]
Clock uncertainty70%DTCDATAIN[63:0]
Clock uncertainty70%DTCDATASEQ
Clock uncertainty70%DTCDATAERREN
Clock uncertainty70%DTCDATAPARITY[7:0]
Clock uncertainty70%DTCTESTEN
Clock uncertainty70%ITCDATAEN0
Clock uncertainty70%ITCDATAEN1
Clock uncertainty70%ITCDATAWRITE
Clock uncertainty70%ITCDATABYTEWR[7:0]
Clock uncertainty70%ITCDATAADDR[17:3]
Clock uncertainty70%ITCDATAIN[63:0]
Clock uncertainty70%ITCDATASEQ
Clock uncertainty70%ITCDATAERREN
Clock uncertainty70%ITCDATAPARITY[7:0]
Clock uncertainty70%I ITCTESTEN
Clock uncertainty20%SO*
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