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Copyright © 2005-2007 ARM Limited. All rights reserved.
Table of Contents
LDRB
LDRH
LDR
or LDM
1
LDRD
or LDM
2
LDM
3
LDM
4
LDM
5
LDM
6
LDM
7
LDM
8
LDM
9
LDM
10
LDM
11
LDM
12
LDM
13
LDM
14
LDM
15
LDM
16
STRB
STRH
STR
or STM
1
STRD
or STM
2
STM
3
STM
4
STM
5
STM
6
STM
7
STM
8
STM
9
STM
10
STM
11
STM
12
STM
13
STM
14
STM
15
STM
16
List of Figures
List of Tables
LDRB
LDRH
LDR
or LDM
1LDRD
or LDM
2LDRD
or LDM
2 fromword 7LDM
3, Strongly Ordered or DevicememoryLDM
3, Noncacheable memory or cachedisabledLDM
3 from word 6, or 7LDM
4, Strongly Ordered or DevicememoryLDM
4, Noncacheable memory or cachedisabledLDM
4 from word 5, 6, or 7LDM
5, Strongly Ordered or DevicememoryLDM
5, Noncacheable memory or cachedisabledLDM
5 from word 4, 5, 6, or 7LDM
6, Strongly Ordered or DevicememoryLDM
6, Noncacheable memory or cachedisabledLDM
6 from word 3, 4, 5, 6, or 7LDM
7, Strongly Ordered or DevicememoryLDM
7, Noncacheable memory or cachedisabledLDM
7 from word 2, 3, 4, 5, 6, or7LDM
9LDM
10LDM
13LDM
14LDM
15LDM
16STRB
STRH
STR
or STM
1STRD
or STM
2 towords 0 to 6STRD
or STM
2to word 7STM
3to words 0, 1, 2, 3, 4, or 5STM
3to words 6 or 7STM
4to word 0, 1, 2, 3, or 4STM
4to word 5, 6, or 7STM
5to word 0, 1, 2, or 3STM
5to word 4, 5, 6, or 7STM
6to word 0, 1, or 2STM
6to word 3, 4, 5, 6, or 7STM
7to word 0 or 1STM
7to words 2 to 7STM
8to word 0STM
8to words 1 to 7STM
9STM
12STM
13STM
14STM
15STM
16QADD
, QDADD
, QSUB
,and QDSUB
instruction cycle timing behavior<addr_md_1cycle>
and <addr_md_2cycle>
LDR
example instruction explanation <addr_md_1cycle>
and <addr_md_2cycle>
LDRD
example instruction explanationRFE
and SRS
instructions cycletiming behaviorProprietaryNotice
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Neither the whole nor any part of the information containedin, or the product described in, this document may be adapted orreproduced in any material form except with the prior written permissionof the copyright holder.
The product described in this document is subject to continuousdevelopments and improvements. All particulars of the product andits use contained in this document are given by ARM in good faith.However, all warranties implied or expressed, including but notlimited to implied warranties of merchantability, or fitness forpurpose, are excluded.
This document is intended only to assist the reader in theuse of the product. ARM Limited shall not be liable for any lossor damage arising from the use of any information in this document,or any error or omission in such information, or any incorrect useof the product.
Figure 14.1 reprintedwith permission from IEEE Std. 1149.1-2001, IEEE StandardTest Access Port and Boundary-Scan Architecture by IEEEStd. The IEEE disclaims any responsibility or liability resultingfrom the placement and use in the described manner.
Some material in this document is based on IEEEStandard for Binary Floating-Point Arithmetic , ANSI/IEEE Std754-1985. The IEEE disclaims any responsibility or liability resultingfrom the placement and use in the described manner.
Revision History | ||
---|---|---|
Revision A | 10March 2005 | First release for r0p0. |
Revision B | 03October 2005 | Second release for r0p0. Enhancementto text. |
Revision C | 10October 2005 | Third release for r0p0. Enhancementto figures. |
Revision D | 28June 2006 | First release for r0p2. |
Revision E | 30June 2006 | Second release for r0p2. Enhancementto text. |
Revision F | 31May 2007 | First release for r0p4. Enhancement totext and figures. |
Revision G | 31July 2007 | Confidentiality changed to Non-Confidential.No change to contents. |