Embedded Cross Trigger Technical Reference Manual 3.3.15. Peripheral Identification Registers, CTIPERIPHID0-3

3.3.15. Peripheral Identification Registers, CTIPERIPHID0-3

CTIPERIPHID0-3 are read-only registers. These registers are four 8-bit registers that span address locations 0xFE0-0xFEC. The registers can conceptually be treated as a single 32-bit register. The read-only registers provide the following options for the peripheral:

Part number [11:0]: This identifies the peripheral. The three digit product code 0x900 is used for the CTI.
Designer [19:12]: This is the identification of the designer. ARM Ltd is 0x41 (ASCII A).
Revision number [23:20]: This is the revision number of the peripheral. The revision number starts from 0, and the value is revision dependent.
Configuration [31:24]: This is the configuration option of the peripheral. The configuration value is 0.

Figure 3.1 shows the bit assignments for the Peripheral Identification Registers.

Figure 3.1. Peripheral Identification Registers bit assignments

The four 8-bit peripheral identification registers are described in the following sections:

CTIPERIPHID0 Register

This register is hard-coded and the fields within the register determine the reset value. This register can be accessed with three wait states. Table 3.16shows the bit assignments for the CTIPERIPHID0 Register.

Table 3.16. CTIPERIPHID0 Register bit assignments

Bits	Name	Description
[31:8]	Reserved	Reserved. read as zero, do not modify.
[7:0]	Partnumber0	These bits read back as `0x00`.

CTIPERIPHID1 Register

This register is hard-coded and the fields within the register determine the reset value. This register can be accessed with three wait states. Table 3.17 shows the bit assignments for the CTIPERIPHID1 Register.

Table 3.17. CTIPERIPHID1 Register bit assignments

Bits	Name	Description
[31:8]	Reserved	Reserved. read as zero, do not modify
[7:4]	Designer0	These bits read back as `0x1`
[3:0]	Partnumber1	These bits read back as `0x9`

CTIPERIPHID2 Register

This register is hard-coded and the fields within the register determine the reset value. This register can be accessed with three wait states. Table 3.18 shows the bit assignments for the CTIPERIPHID2 Register.

Table 3.18. CTIPERIPHID2 Register bit assignments

Bits	Name	Description
[31:8]	Reserved	Reserved. read as zero, do not modify.
[7:4]	Revision	These bits read back as the revision number, which can be between 0 and 15
[3:0]	Designer1	These bits read back as `0x4`

CTIPERIPHID3 Register

This register is hard-coded and the fields within the register determine the reset value. This register can be accessed with three wait states. Table 3.19 shows the bit assignments for the CTIPERIPHID3 Register.

Table 3.19. CTIPERIPHID3 Register bit assignments

Bits	Name	Description
[31:8]	Reserved	Reserved. read as zero, do not modify
[7:2]	Configuration	These bits read back as `0x0`
[1:0]	Configuration	Indicates the number of interrupts supported: 00 = 32 (default) 01 = 64 10 = 256

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