Embedded Cross Trigger Technical Reference Manual

Revision: r0p0


Table of Contents

Preface
About this book
Intended audience
Using this book
Product revision status
Typographical conventions
Other conventions
Further reading
Feedback
Feedback on the ECT
Feedback on this book
1. Introduction
1.1. About the ARM debug system
1.1.1. Debug system overview
1.1.2. Development tools
1.2. About the ECT
1.2.1. Features of the ECT
1.2.2. Trigger input events
1.2.3. Events
2. Functional Description
2.1. Functional overview
2.1.1. About the ECT system
2.1.2. Interfaces handshake protocol
2.1.3. Synchronization
2.1.4. Clock information
2.1.5. Mapping
2.2. Trigger interface
2.2.1. About the TI
2.2.2. ECTTRIGIN handshake
2.2.3. Trigger interface wrapper input
2.2.4. ECTTRIGOUT handshake
2.2.5. Cross trigger events
2.2.6. Example wrapper
2.3. Channel interface
2.3.1. About the CI
2.3.2. ECTCHIN handshake
2.3.3. ECTCHOUT handshake
2.3.4. Channel interface connections
2.4. AHB interface
2.5. CTI register access
2.5.1. Access issues
2.6. ECT registers
2.6.1. Application trigger
2.6.2. Possible system deadlock situation to avoid
3. Programmer’s Model
3.1. About the programmer’s model
3.2. Summary of CTI registers
3.3. Register descriptions
3.3.1. CTI Control Register, CTICONTROL
3.3.2. CTI Status Register, CTISTATUS
3.3.3. CTI Lock Enable Register, CTILOCK
3.3.4. CTI Protection Enable Register, CTIPROTECTION
3.3.5. CTI Interrupt Acknowledge Register, CTIINTACK
3.3.6. CTI Application Trigger Set Register, CTIAPPSET
3.3.7. CTI Application Trigger Clear Register, CTIAPPCLEAR
3.3.8. CTI Application Pulse Register, CTIAPPPULSE
3.3.9. CTI Trigger to Channel Enable Registers, CTIINEN0-7
3.3.10. CTI Channel to Trigger Enable Registers, CTIOUTEN0-7
3.3.11. CTI Trigger In Status Register, CTITRIGINSTATUS
3.3.12. CTI Trigger Out Status Register, CTITRIGOUTSTATUS
3.3.13. CTI Channel In Status Register, CTICHINSTATUS
3.3.14. CTI Channel Out Status Register, CTICHOUTSTATUS
3.3.15. Peripheral Identification Registers, CTIPERIPHID0-3
3.3.16. Identification Registers, CTIPCELLID0-3
4. Programmer’s Model for Test
4.1. ECT/CTI test harness overview
4.2. Scan testing
4.3. Test registers
4.3.1. CTIITCR Register
4.3.2. CTIITIP0 Register
4.3.3. CTIITIP1 Register
4.3.4. CTIITIP2 Register
4.3.5. CTIITIP3 Register
4.3.6. CTIITOP0 Register
4.3.7. CTIITOP1 Register
4.3.8. CTIITOP2 Register
4.3.9. CTIITOP3 Register
A. Signal Descriptions
A.1. ECT CTI AMBA AHB signals
A.2. ECT clock, enable, and reset signals
A.3. ECT synchronization bypass signals
A.4. ECT CTI subsystem signals
A.5. ECT channel interface signals
A.6. Scan test control signals
B. Timing Requirements
B.1. AHB interface timing
B.2. ECTCTMCLK domain timing
B.3. ECTCTICLK domain timing
Glossary

List of Tables

2.1. Bypass modes
2.2. Example subsystem wrapper inputs
2.3. Example subsystem wrapper outputs
3.1. CTI register summary
3.2. CTI Control Register bit assignments
3.3. CTI Status Register bit assignments
3.4. CTI Lock Enable Register bit assignments
3.5. CTI Protection Enable Register bit assignments
3.6. CTI Interrupt Acknowledge Register bit assignments
3.7. CTI Application Trigger Set Register bit assignments
3.8. CTI Application Trigger Clear Register bit assignments
3.9. CTI Application Pulse Register bit assignments
3.10. CTI Trigger to Channel Enable Registers bit assignments
3.11. CTI Channel to Trigger Enable Registers bit assignments
3.12. CTI Trigger In Status Register bit assignments
3.13. CTI Trigger Out Status Register bit assignments
3.14. CTI Channel In Status Register bit assignments
3.15. CTI Channel Out Status Register bit assignments
3.16. CTIPERIPHID0 Register bit assignments
3.17. CTIPERIPHID1 Register bit assignments
3.18. CTIPERIPHID2 Register bit assignments
3.19. CTIPERIPHID3 Register bit assignments
3.20. CTIPCELLID0 Register bit assignments
3.21. CTIPCELLID1 Register bit assignments
3.22. CTIPCELLID2 Register bit assignments
3.23. CTIPCELLID3 Register bit assignments
4.1. Test registers memory map
4.2. CTIITCR Register bit assignments
4.3. CTIITIP0 Register bit assignments
4.4. CTIITIP1 Register bit assignments
4.5. CTIITIP2 Register bit assignments
4.6. CTIITIP3 Register bit assignments
4.7. CTIITOP0 Register bit assignments
4.8. CTIITOP1 Register bit assignments
4.9. CTIITOP2 Register bit assignments
4.10. CTIITOP3 Register bit assignments
A.1. ECT CTI AMBA AHB signals
A.2. Clock, enable, and reset signals
A.3. CTI synchronization bypass signals
A.4. ECT CTI subsystem signals
A.5. ECT channel interface signals
A.6. Scan test control signals
B.1. AHB interface timing requirements
B.2. ECTCTMCLK domain timing requirements
B.3. ECTCTICLK domain timing requirements

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Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.

The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision A22 July 2003First issue for r0p0
Copyright © 2003. All rights reserved.ARM DDI 0291A
Non-Confidential