PrimeCell ® ColorLCD Controller (PL111) Technical Reference Manual

Revision:r0p2


Table of Contents

Preface
About this manual
Product revision status
Intended audience
Organization
Conventions
Further reading
Feedback
Feedback on this product
Feedback on this manual
1. Introduction
1.1. About the controller
1.1.1. Features of the controller
1.1.2. Programmable parameters
1.1.3. Target markets
1.1.4. LCD panel resolution
1.1.5. Hardware cursor support
1.1.6. Types of LCD panel supported
1.1.7. Number of colors supported
1.1.8. LCD powering up and powering down sequencesupport
1.2. Product revisions
2. Functional Overview
2.1. Controller overview
2.2. AHB interfaces
2.2.1. AHB slave interface
2.2.2. AHB master interface
2.2.3. Bus architecture
2.3. Dual DMA FIFOs and associated controllogic
2.4. Pixel serializer
2.5. RAM palette
2.6. Hardware cursor
2.6.1. Integration with the controller
2.6.2. Operation
2.6.3. Supported cursor sizes
2.6.4. Movement
2.6.5. Image format
2.7. Gray scaler
2.8. Upper and lower panel formatters
2.9. Panel clock generator
2.10. Timing controller
2.11. STN and TFT data select
2.12. Interrupt generation
3. Programmer’s Model
3.1. About the programmer’s model
3.2. Register summary
3.3. Register descriptions
3.3.1. Horizontal Axis Panel Control Register
3.3.2. Vertical Axis Panel Control Register
3.3.3. Clock and Signal Polarity Control Register
3.3.4. Line End Control Register
3.3.5. Upper and Lower Panel Frame Base AddressRegisters
3.3.6. LCD Control Register
3.3.7. Interrupt Mask Set/Clear Register
3.3.8. Raw Interrupt Status Register
3.3.9. Masked Interrupt Status Register
3.3.10. LCD Interrupt Clear Register
3.3.11. LCD Upper and Lower Panel Current AddressValue Registers
3.3.12. 256x16-bit Color Palette Registers
3.3.13. Cursor Image RAM Register
3.3.14. Cursor Control Register
3.3.15. Cursor Configuration Register
3.3.16. Cursor Palette Registers
3.3.17. Cursor XY Position Register
3.3.18. Cursor Clip PositionRegister
3.3.19. Cursor Interrupt Mask Set/Clear Register
3.3.20. Cursor Interrupt Clear Register
3.3.21. Cursor Raw Interrupt Status Register
3.3.22. Cursor Masked Interrupt Status Register
3.3.23. Peripheral Identification Registers
3.3.24. PrimeCell IdentificationRegisters
3.4. Interrupts
3.4.1. Master bus error interrupt, CLCDMBEINTR
3.4.2. Vertical compare interrupt, CLCDVCOMPINTR
3.4.3. Next base address update interrupt,CLCDLNBUINTR
3.4.4. FIFO underflow interrupt, CLCDFUFINTR
4. Programmer’s Model for Test
4.1. Scan testing
4.2. Test registers
4.2.1. Integration Test Control Register
4.2.2. Integration Test Output Register 1
4.2.3. Integration Test Output Register 2
A. Signal Descriptions
A.1. AHB slave interface signals
A.2. AHB master interface signals
A.2.1. HBURSTM and HRESPM signals
A.2.2. Steady state signals
A.3. External pad interface signals
A.4. On-chip signals
A.5. Scan signals
A.6. LCD panel signal multiplexing details
Glossary

List of Figures

1. Key to timing diagram conventions
1.1. Power-up and power-down sequences
2.1. CLCDC block diagram
2.2. Single-bus AHB architecture
2.3. Dual-bus AHB architecture
2.4. LBLP, DMA FIFO output bits [31:16]
2.5. LBLP, DMA FIFO output bits [15:0]
2.6. BBBP, DMA FIFO output bits [31:16]
2.7. BBBP, DMA FIFO output bits [15:0]
2.8. LBBP, DMA FIFO output bits [31:16]
2.9. LBBP, DMA FIFO output bits [15:0]
2.10. Hardware cursor block diagram
2.11. Hardware cursor movement
2.12. Hardware cursor clipping
2.13. Hardware cursor image format
3.1. LCDTiming0 Register bit assignments
3.2. LCDTiming1 Register bit assignments
3.3. LCDTiming2 Register bit assignments
3.4. LCDTiming3 Register bit assignments
3.5. LCDUPBASE Register bit assignments
3.6. LCDLPBASE Register bit assignments
3.7. LCDControl Register bit assignments
3.8. LCDIMSC Register bit assignments
3.9. LCDRIS Register bit assignments
3.10. LCDMIS Register bit assignments
3.11. LCDICR Register bit assignments
3.12. LCDPalette Register bit assignments
3.13. ClcdCrsrCtrl Register bit assignments
3.14. ClcdCrsrConfig Register bit assignments
3.15. ClcdCrsrPalette0 and ClcdCrsrPalette1Register bit assignments
3.16. ClcdCrsrXY Register bit assignments
3.17. ClcdCrsrClip Register bit assignments
3.18. ClcdCrsrIMSC Register bit assignments
3.19. ClcdCrsrICR Register bit assignments
3.20. ClcdCrsrRIS Register bit assignments
3.21. ClcdCrsrMIS Register bit assignments
3.22. CLCDPeriphID0-3 Register bit assignments
3.23. CLCDPeriphID0 Register bit assignments
3.24. CLCDPeriphID1 Register bit assignments
3.25. CLCDPeriphID2 Register bit assignments
3.26. CLCDPeriphID3 Register bit assignments
3.27. CLCDPCellID0-3 Register bit assignments
3.28. CLCDPCellID0 Register bit assignments
3.29. CLCDPCellID1 Register bit assignments
3.30. CLCDPCellID2 Register bit assignments
3.31. CLCDPCellID3 Register bit assignments
4.1. LCDTCR Register bit assignments
4.2. LCDITOP1 Register bit assignments
4.3. LCDITOP2 Register bit assignments

List of Tables

2.1. RGB mode data format
2.2. Palette data storage mode
2.3. Palette data storage for STN modes
2.4. Supported cursor images
2.5. 32x32 cursor base addresses
2.6. LBBP buffer to pixel mapping 32x32 Cursor0 for datawords[31:16]
2.7. LBBP buffer to pixel mapping 32x32 Cursor0 for datawords[15:0]
2.8. LBBP buffer to pixel mapping 64x64 for datawords [31:16]
2.9. LBBP buffer to pixel mapping 64x64 for datawords [15:0]
2.10. 32x32 software mask storage
2.11. 64x64 software mask storage
2.12. Pixel encoding
2.13. Color display driven with 2 2 /3 pixeldata in repeating sequence
3.1. Register summary
3.2. LCDTiming0 Register bit assignments
3.3. LCDTiming1 Register bit assignments
3.4. LCDTiming2 Register bit assignments
3.5. LCDTiming3 Register bit assignments
3.6. LCDUPBASE Register bit assignments
3.7. LCDLPBASE Register bit assignments
3.8. LCDControl Register bit assignments
3.9. LCDIMSC Register bit assignments
3.10. LCDRIS Register bit assignments
3.11. LCDMIS Register bit assignments
3.12. LCDICR Register bit assignments
3.13. LCDPalette Register bit assignments
3.14. ClcdCrsrCtrl Register bit assignments
3.15. ClcdCrsrConfig Register bit assignments
3.16. ClcdCrsrPalette Register bit assignments
3.17. ClcdCrsrXY Register bit assignments
3.18. ClcdCrsrClip Register bit assignments
3.19. ClcdCrsrIMSC Register bit assignments
3.20. ClcdCrsrICR Register bit assignments
3.21. ClcdCrsrRIS Register bit assignments
3.22. ClcdCrsrMIS Register bit assignments
3.23. Peripheral Identification Register options
3.24. CLCDPeriphID0 Register bit assignments
3.25. CLCDPeriphID1 Register bit assignments
3.26. CLCDPeriphID2 Register bit assignments
3.27. CLCDPeriphID3 Register bit assignments
3.28. CLCDPCellID0 Register bit assignments
3.29. CLCDPCellID1 Register bit assignments
3.30. CLCDPCellID2 Register bit assignments
3.31. CLCDPCellID3 Register bit assignments
4.1. Test register summary
4.2. LCDTCR Register bit assignments
4.3. LCDITOP1 Register bit assignments
4.4. LCDITOP2 Register bit assignments
A.1. AHB slave interface signals
A.2. HRESPS bus
A.3. AHB master interface signals
A.4. HBURSTM and HRESPM signals
A.5. Steady state signals
A.6. External pad interface signals
A.7. On-chip signals
A.8. Scan signals
A.9. STN panel signal multiplexing
A.10. TFT panel signal multiplexing

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The product described in this document is subject to continuousdevelopments and improvements. All particulars of the product andits use contained in this document are given by ARM in good faith.However, all warranties implied or expressed, including but notlimited to implied warranties of merchantability, or fitness forpurpose, are excluded.

This document is intended only to assist the reader in theuse of the product. ARM Limited shall not be liable for any lossor damage arising from the use of any information in this document,or any error or omission in such information, or any incorrect useof the product.

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ConfidentialityStatus

This document is Non-Confidential. The right to use, copyand disclose this document may be subject to license restrictionsin accordance with the terms of the agreement entered into by ARMand the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developedproduct.

Revision History
Revision A 14October 2003 First release.
Revision B 24July 2006 Update to r0p1.Corrections to:Table 2‑3on page 2‑14Table A‑7 on page A‑6Table A‑9 on page A‑8.Improvedexplanations for:pixels-per-line in Table 3‑2 on page 3‑5clocks-per-linein Table 3‑4 on page 3‑8.
Revision C 22 December2006 First release for r0p2.
Copyright © 2003, 2006 ARM Limited. All rights reserved. ARM DDI 0293C
Non-Confidential