ARM1176JZF-S™ Technical Reference Manual

Revision: r0p7


Table of Contents

Preface
About this book
Product revision status
Intended audience
Using this book
Conventions
Additional reading
Feedback
Feedback on this product
Feedback on content
1. Introduction
1.1. About the processor
1.2. Extensions to ARMv6
1.3. TrustZone security extensions
1.4. ARM1176JZF-S architecture with Jazelle technology
1.4.1. Instruction compression
1.4.2. The Thumb instruction set
1.4.3. Java bytecodes
1.5. Components of the processor
1.5.1. Integer core
1.5.2. Load Store Unit (LSU)
1.5.3. Prefetch unit
1.5.4. Memory system
1.5.5. AMBA AXI interface
1.5.6. Coprocessor interface
1.5.7. Debug
1.5.8. Instruction cycle summary and interlocks
1.5.9. Vector Floating-Point (VFP)
1.5.10. System control
1.5.11. Interrupt handling
1.6. Power management
1.7. Configurable options
1.8. Pipeline stages
1.9. Typical pipeline operations
1.9.1. Instruction progression
1.10. ARM1176JZF-S instruction set summary
1.10.1. Extended ARM instruction set summary
1.10.2. Thumb instruction set summary
1.11. Product revisions
2. Programmer’s Model
2.1. About the programmer’s model
2.2. Secure world and Non-secure world operation with TrustZone
2.2.1. TrustZone model
2.2.2. How the Secure model works
2.2.3. TrustZone write access disable
2.2.4. Secure Monitor bus
2.3. Processor operating states
2.3.1. Switching state
2.3.2. Interworking ARM and Thumb state
2.4. Instruction length
2.5. Data types
2.6. Memory formats
2.6.1. Legacy big-endian format
2.6.2. Little-endian format
2.7. Addresses in a processor system
2.8. Operating modes
2.9. Registers
2.9.1. The ARM state core register set
2.9.2. The Thumb state core register set
2.9.3. Accessing high registers in Thumb state
2.9.4. ARM state and Thumb state registers relationship
2.10. The program status registers
2.10.1. The condition code flags
2.10.2. The Q flag
2.10.3. The J bit
2.10.4. The GE[3:0] bits
2.10.5. The E bit
2.10.6. The A bit
2.10.7. The control bits
2.10.8. Modification of PSR bits by MSR instructions
2.10.9. Reserved bits
2.11. Additional instructions
2.11.1. Load or Store Byte Exclusive
2.11.2. Load or Store Halfword Exclusive
2.11.3. Load or Store Doubleword
2.11.4. CLREX
2.11.5. NOP-compatible hints
2.12. Exceptions
2.12.1. New instructions for exception handling
2.12.2. Exception entry and exit summary
2.12.3. Entering an ARM exception
2.12.4. Leaving an ARM exception
2.12.5. Reset
2.12.6. Fast interrupt request
2.12.7. Interrupt request
2.12.8. Low interrupt latency configuration
2.12.9. Interrupt latency example
2.12.10. Aborts
2.12.11. Imprecise Data Abort mask in the CPSR/SPSR
2.12.12. Supervisor call instruction
2.12.13. Secure Monitor Call (SMC)
2.12.14. Undefined instruction
2.12.15. Breakpoint instruction (BKPT)
2.12.16. Exception vectors
2.12.17. Exception priorities
2.13. Software considerations
2.13.1. Branch Target Address Cache flush
2.13.2. Waiting for DMA to complete
3. System Control Coprocessor
3.1. About the system control coprocessor
3.1.1. System control coprocessor functional groups
3.1.2. System control and configuration
3.1.3. MMU control and configuration
3.1.4. Cache control and configuration
3.1.5. TCM control and configuration
3.1.6. Cache Master Valid Registers
3.1.7. DMA control
3.1.8. System performance monitor
3.1.9. System validation
3.1.10. Use of the system control coprocessor
3.2. System control processor registers
3.2.1. Register allocation
3.2.2. c0, Main ID Register
3.2.3. c0, Cache Type Register
3.2.4. c0, TCM Status Register
3.2.5. c0, TLB Type Register
3.2.6. c0, CPUID registers
3.2.7. c1, Control Register
3.2.8. c1, Auxiliary Control Register
3.2.9. c1, Coprocessor Access Control Register
3.2.10. c1, Secure Configuration Register
3.2.11. c1, Secure Debug Enable Register
3.2.12. c1, Non-Secure Access Control Register
3.2.13. c2, Translation Table Base Register 0
3.2.14. c2, Translation Table Base Register 1
3.2.15. c2, Translation Table Base Control Register
3.2.16. c3, Domain Access Control Register
3.2.17. c5, Data Fault Status Register
3.2.18. c5, Instruction Fault Status Register
3.2.19. c6, Fault Address Register
3.2.20. c6, Watchpoint Fault Address Register
3.2.21. c6, Instruction Fault Address Register
3.2.22. c7, Cache operations
3.2.23. c8, TLB Operations Register
3.2.24. c9, Data and instruction cache lockdown registers
3.2.25. c9, Data TCM Region Register
3.2.26. c9, Instruction TCM Region Register
3.2.27. c9, Data TCM Non-secure Control Access Register
3.2.28. c9, Instruction TCM Non-secure Control Access Register
3.2.29. c9, TCM Selection Register
3.2.30. c9, Cache Behavior Override Register
3.2.31. c10, TLB Lockdown Register
3.2.32. c10, Memory region remap registers
3.2.33. c11, DMA identification and status registers
3.2.34. c11, DMA User Accessibility Register
3.2.35. c11, DMA Channel Number Register
3.2.36. c11, DMA enable registers
3.2.37. c11, DMA Control Register
3.2.38. c11, DMA Internal Start Address Register
3.2.39. c11, DMA External Start Address Register
3.2.40. c11, DMA Internal End Address Register
3.2.41. c11, DMA Channel Status Register
3.2.42. c11, DMA Context ID Register
3.2.43. c12, Secure or Non-secure Vector Base Address Register
3.2.44. c12, Monitor Vector Base Address Register
3.2.45. c12, Interrupt Status Register
3.2.46. c13, FCSE PID Register
3.2.47. c13, Context ID Register
3.2.48. c13, Thread and process ID registers
3.2.49. c15, Peripheral Port Memory Remap Register
3.2.50. c15, Secure User and Non-secure Access Validation Control Register
3.2.51. c15, Performance Monitor Control Register
3.2.52. c15, Cycle Counter Register
3.2.53. c15, Count Register 0
3.2.54. c15, Count Register 1
3.2.55. c15, System Validation Counter Register
3.2.56. c15, System Validation Operations Register
3.2.57. c15, System Validation Cache Size Mask Register
3.2.58. c15, Instruction Cache Master Valid Register
3.2.59. c15, Data Cache Master Valid Register
3.2.60. c15, TLB lockdown access registers
4. Unaligned and Mixed-endian Data Access Support
4.1. About unaligned and mixed-endian support
4.2. Unaligned access support
4.2.1. Legacy support
4.2.2. ARMv6 extensions
4.2.3. Legacy and ARMv6 configurations
4.2.4. Legacy data access in ARMv6 (U=0)
4.2.5. Support for unaligned data access in ARMv6 (U=1)
4.2.6. ARMv6 unaligned data access restrictions
4.3. Endian support
4.3.1. Load unsigned byte, endian independent
4.3.2. Load signed byte, endian independent
4.3.3. Store byte, endian independent
4.3.4. Load unsigned halfword, little-endian
4.3.5. Load unsigned halfword, big-endian
4.3.6. Load signed halfword, little-endian
4.3.7. Load signed halfword, big-endian
4.3.8. Store halfword, little-endian
4.3.9. Store halfword, big-endian
4.3.10. Load word, little-endian
4.3.11. Load word, big-endian
4.3.12. Store word, little-endian
4.3.13. Store word, big-endian
4.3.14. Load double, load multiple, load coprocessor (little-endian, E = 0)
4.3.15. Load double, load multiple, load coprocessor (big-endian, E=1)
4.3.16. Store double, store multiple, store coprocessor (little-endian, E=0)
4.3.17. Store double, store multiple, store coprocessor (big-endian, E=1)
4.4. Operation of unaligned accesses
4.5. Mixed-endian access support
4.5.1. Legacy fixed instruction and data endianness
4.5.2. ARMv6 support for mixed-endian data
4.5.3. Reset values of the U, B, and EE bits
4.6. Instructions to reverse bytes in a general-purpose register
4.6.1. All load and store operations
4.7. Instructions to change the CPSR E bit
5. Program Flow Prediction
5.1. About program flow prediction
5.2. Branch prediction
5.2.1. Enabling program flow prediction
5.2.2. Dynamic branch predictor
5.2.3. Static branch predictor
5.2.4. Branch folding
5.2.5. Incorrect predictions and correction
5.3. Return stack
5.4. Memory Barriers
5.4.1. Instruction Memory Barriers (IMBs)
5.5. ARM1176JZF-S IMB implementation
5.5.1. Execution of IMB instructions
6. Memory Management Unit
6.1. About the MMU
6.2. TLB organization
6.2.1. MicroTLB
6.2.2. Main TLB
6.2.3. TLB control operations
6.2.4. Page-based attributes
6.2.5. Supersections
6.3. Memory access sequence
6.3.1. TLB match process
6.3.2. Virtual to physical translation mapping restrictions
6.3.3. Tightly-Coupled Memory
6.4. Enabling and disabling the MMU
6.4.1. Enabling the MMU
6.4.2. Disabling the MMU
6.4.3. Behavior with MMU disabled
6.5. Memory access control
6.5.1. Domains
6.5.2. Access permissions
6.5.3. Execute never bits in the TLB entry
6.6. Memory region attributes
6.6.1. C and B bit, and type extension field encodings
6.6.2. Shared
6.6.3. NS attribute
6.7. Memory attributes and types
6.7.1. Normal memory attribute
6.7.2. Device memory attribute
6.7.3. Strongly Ordered memory attribute
6.7.4. Ordering requirements for memory accesses
6.7.5. Explicit Memory Barriers
6.7.6. Backwards compatibility
6.8. MMU aborts
6.8.1. External aborts
6.9. MMU fault checking
6.9.1. Fault checking sequence
6.9.2. Alignment fault
6.9.3. Translation fault
6.9.4. Access bit fault
6.9.5. Domain fault
6.9.6. Permission fault
6.9.7. Debug event
6.10. Fault status and address
6.11. Hardware page table translation
6.11.1. Backwards-compatible page table translation subpage AP bits enabled
6.11.2. ARMv6 page table translation subpage AP bits disabled
6.11.3. Restrictions on page table mappings page coloring
6.12. MMU descriptors
6.12.1. First-level descriptor address
6.12.2. First-level descriptor
6.12.3. Second-level page table walk
6.13. MMU software-accessible registers
7. Level One Memory System
7.1. About the level one memory system
7.2. Cache organization
7.2.1. Features of the cache system
7.2.2. Cache functional description
7.2.3. Cache control operations
7.2.4. Cache miss handling
7.2.5. Cache disabled behavior
7.2.6. Unexpected hit behavior
7.3. Tightly-coupled memory
7.3.1. TCM behavior
7.3.2. Restriction on page table mappings
7.3.3. Restriction on page table attributes
7.4. DMA
7.5. TCM and cache interactions
7.5.1. Overlapping between TCM regions
7.5.2. DMA and core access arbitration
7.5.3. Instruction accesses to TCM
7.5.4. Data accesses to the Instruction TCM
7.6. Write buffer
8. Level Two Interface
8.1. About the level two interface
8.1.1. AXI parameters for the level 2 interconnect interfaces
8.1.2. Level two instruction-side controller
8.1.3. Level two data-side controller
8.1.4. DMA
8.2. Synchronization primitives
8.2.1. Load-exclusive instruction
8.2.2. Store-exclusive instruction
8.2.3. Example of LDREX and STREX usage
8.3. AXI control signals in the processor
8.3.1. Channel definition
8.3.2. Signal name suffixes
8.3.3. Address channel signals
8.4. Instruction Fetch Interface transfers
8.4.1. Cacheable fetches
8.4.2. Noncacheable fetches
8.5. Data Read/Write Interface transfers
8.5.1. Linefills
8.5.2. Noncacheable LDRB
8.5.3. Noncacheable LDRH
8.5.4. Noncacheable LDR or LDM1
8.5.5. Noncacheable LDRD or LDM2
8.5.6. Noncacheable LDM3
8.5.7. Noncacheable LDM4
8.5.8. Noncacheable LDM5
8.5.9. Noncacheable LDM6
8.5.10. Noncacheable LDM7
8.5.11. Noncacheable LDM8
8.5.12. Noncacheable LDM9
8.5.13. Noncacheable LDM10
8.5.14. Noncacheable LDM11
8.5.15. Noncacheable LDM12
8.5.16. Noncacheable LDM13
8.5.17. Noncacheable LDM14
8.5.18. Noncacheable LDM15
8.5.19. Noncacheable LDM16
8.5.20. Half-line Write-Back
8.5.21. Full-line Write-Back
8.5.22. Cacheable Write-Through or Noncacheable STRB
8.5.23. Cacheable Write-Through or Noncacheable STRH
8.5.24. Cacheable Write-Through or Noncacheable STR or STM1
8.5.25. Cacheable Write-Through or Noncacheable STRD or STM2
8.5.26. Cacheable Write-Through or Noncacheable STM3
8.5.27. Cacheable Write-Through or Noncacheable STM4
8.5.28. Cacheable Write-Through or Noncacheable STM5
8.5.29. Cacheable Write-Through or Noncacheable STM6
8.5.30. Cacheable Write-Through or Noncacheable STM7
8.5.31. Cacheable Write-Through or Noncacheable STM8
8.5.32. Cacheable Write-Through or Noncacheable STM9
8.5.33. Cacheable Write-Through or Noncacheable STM10
8.5.34. Cacheable Write-Through or Noncacheable STM11
8.5.35. Cacheable Write-Through or Noncacheable STM12
8.5.36. Cacheable Write-Through or Noncacheable STM13
8.5.37. Cacheable Write-Through or Noncacheable STM14
8.5.38. Cacheable Write-Through or Noncacheable STM15
8.5.39. Cacheable Write-Through or Noncacheable STM16
8.6. Peripheral Interface transfers
8.7. Endianness
8.8. Locked access
9. Clocking and Resets
9.1. About clocking and resets
9.2. Clocking and resets with no IEM
9.2.1. Processor clocking with no IEM
9.2.2. Reset with no IEM
9.3. Clocking and resets with IEM
9.3.1. Processor clocking with IEM
9.3.2. Reset with IEM
9.4. Reset modes
9.4.1. Power-on reset
9.4.2. CP14 debug logic
9.4.3. Processor reset
9.4.4. DBGTAP reset
9.4.5. Normal operation
10. Power Control
10.1. About power control
10.2. Power management
10.2.1. Run mode
10.2.2. Standby mode
10.2.3. Shutdown mode
10.2.4. Dormant mode
10.2.5. Communication to the Power Management Controller
10.3. VFP shutdown
10.4. Intelligent Energy Management
10.4.1. Purpose of IEM
10.4.2. Structure of IEM
10.4.3. Operation of IEM
10.4.4. Use of IEM
11. Coprocessor Interface
11.1. About the coprocessor interface
11.2. Coprocessor pipeline
11.2.1. Coprocessor instructions
11.2.2. Coprocessor control
11.2.3. Pipeline synchronization
11.2.4. Pipeline control
11.2.5. Instruction tagging
11.2.6. Flush broadcast
11.3. Token queue management
11.3.1. Queue implementation
11.3.2. Queue modification
11.3.3. Queue flushing
11.4. Token queues
11.4.1. Instruction queue
11.4.2. Length queue
11.4.3. Accept queue
11.4.4. Cancel queue
11.4.5. Finish queue
11.5. Data transfer
11.5.1. Loads
11.5.2. Stores
11.6. Operations
11.6.1. Normal operation
11.6.2. Cancel operations
11.6.3. Bounce operations
11.6.4. Flush operations
11.6.5. Retirement operations
11.7. Multiple coprocessors
11.7.1. Interconnect considerations
11.7.2. Coprocessor selection
11.7.3. Coprocessor switching
12. Vectored Interrupt Controller Port
12.1. About the PL192 Vectored Interrupt Controller
12.2. About the processor VIC port
12.2.1. Synchronization of the VIC port signals
12.2.2. Interrupt handler exit
12.3. Timing of the VIC port
12.3.1. PL192 VIC timing
12.3.2. Core timing
12.4. Interrupt entry flowchart
13. Debug
13.1. Debug systems
13.1.1. The debug host
13.1.2. The protocol converter
13.1.3. The processor
13.2. About the debug unit
13.2.1. Halting debug-mode debugging
13.2.2. Monitor debug-mode debugging
13.2.3. Secure Monitor mode and debug
13.2.4. Virtual addresses and debug
13.2.5. Programming the debug unit
13.3. Debug registers
13.3.1. Accessing debug registers
13.3.2. CP14 c0, Debug ID Register (DIDR)
13.3.3. CP14 c1, Debug Status and Control Register (DSCR)
13.3.4. CP14 c5, Data Transfer Registers (DTR)
13.3.5. CP14 c6, Watchpoint Fault Address Register (WFAR)
13.3.6. CP14 c7, Vector Catch Register (VCR)
13.3.7. CP14 c64-c69, Breakpoint Value Registers (BVR)
13.3.8. CP14 c80-c85, Breakpoint Control Registers (BCR)
13.3.9. CP14 c96-c97, Watchpoint Value Registers (WVR)
13.3.10. CP14 c112-c113, Watchpoint Control Registers (WCR)
13.3.11. CP14 c10, Debug State Cache Control Register
13.3.12. CP14 c11, Debug State MMU Control Register
13.4. CP14 registers reset
13.5. CP14 debug instructions
13.5.1. Executing CP14 debug instructions
13.6. External debug interface
13.7. Changing the debug enable signals
13.8. Debug events
13.8.1. Software debug event
13.8.2. External debug request signal
13.8.3. Halt DBGTAP instruction
13.8.4. Behavior of the processor on debug events
13.8.5. Effect of a debug event on CP15 registers
13.9. Debug exception
13.10. Debug state
13.10.1. Behavior of the PC in Debug state
13.10.2. Interrupts
13.10.3. Exceptions
13.11. Debug communications channel
13.12. Debugging in a cached system
13.12.1. Data cache writes
13.13. Debugging in a system with TLBs
13.14. Monitor debug-mode debugging
13.14.1. Entering the debug monitor target
13.14.2. Setting breakpoints, watchpoints, and vector catch debug events
13.14.3. Setting software breakpoint debug events (BKPT)
13.14.4. Using the debug communications channel
13.15. Halting debug-mode debugging
13.15.1. Entering Debug state
13.15.2. Exiting Debug state
13.15.3. Programming debug events
13.16. External signals
14. Debug Test Access Port
14.1. Debug Test Access Port and Debug state
14.2. Synchronizing RealView ICE
14.3. Entering Debug state
14.4. Exiting Debug state
14.5. The DBGTAP port and debug registers
14.6. Debug registers
14.6.1. Bypass register
14.6.2. Device ID code register
14.6.3. Instruction register
14.6.4. Scan chain select register (SCREG)
14.6.5. Scan chains
14.6.6. Reset
14.7. Using the Debug Test Access Port
14.7.1. Entering and leaving Debug state
14.7.2. Executing instructions in Debug state
14.7.3. Using the ITRsel IR instruction
14.7.4. Transferring data between the host and the core
14.7.5. Using the debug communications channel
14.7.6. Target to host debug communications channel sequence
14.7.7. Host to target debug communications channel
14.7.8. Transferring data in Debug state
14.7.9. Example sequences
14.8. Debug sequences
14.8.1. Debug macros
14.8.2. General setup
14.8.3. Forcing the processor to halt
14.8.4. Entering Debug state
14.8.5. Leaving Debug state
14.8.6. Reading a current mode ARM register in the range R0-R14
14.8.7. Writing a current mode ARM register in the range R0-R14
14.8.8. Reading the CPSR/SPSR
14.8.9. Writing the CPSR/SPSR
14.8.10. Reading the PC
14.8.11. Writing the PC
14.8.12. General notes about reading and writing memory
14.8.13. Reading memory as words
14.8.14. Writing memory as words
14.8.15. Reading memory as halfwords or bytes
14.8.16. Writing memory as halfwords/bytes
14.8.17. Coprocessor register reads and writes
14.8.18. Reading coprocessor registers
14.8.19. Writing coprocessor registers
14.9. Programming debug events
14.9.1. Reading registers using scan chain 7
14.9.2. Writing registers using scan chain 7
14.9.3. Setting breakpoints, watchpoints and vector traps
14.9.4. Setting software breakpoints
14.10. Monitor debug-mode debugging
14.10.1. Receiving data from the core
14.10.2. Sending data to the core
15. Trace Interface Port
15.1. About the ETM interface
15.1.1. Instruction interface
15.1.2. Secure control bus
15.1.3. Data address interface
15.1.4. Data value interface
15.1.5. Pipeline advance interface
15.1.6. Coprocessor interface
15.1.7. Other connections to the core
16. Cycle Timings and Interlock Behavior
16.1. About cycle timings and interlock behavior
16.1.1. Changes in instruction flow overview
16.1.2. Instruction execution overview
16.1.3. Conditional instructions
16.1.4. Opposite condition code checks
16.1.5. Definition of terms
16.2. Register interlock examples
16.3. Data processing instructions
16.3.1. Cycle counts if destination is not PC
16.3.2. Cycle counts if destination is the PC
16.3.3. Example interlocks
16.4. QADD, QDADD, QSUB, and QDSUB instructions
16.5. ARMv6 media data-processing
16.6. ARMv6 Sum of Absolute Differences (SAD)
16.6.1. Example interlocks
16.7. Multiplies
16.8. Branches
16.9. Processor state updating instructions
16.10. Single load and store instructions
16.10.1. Base register update
16.11. Load and Store Double instructions
16.12. Load and Store Multiple Instructions
16.12.1. Load and Store Multiples, other than load multiples including the PC
16.12.2. Load Multiples, where the PC is in the register list
16.12.3. Example Interlocks
16.13. RFE and SRS instructions
16.14. Synchronization instructions
16.15. Coprocessor instructions
16.16. SVC, SMC, BKPT, Undefined, and Prefetch Aborted instructions
16.17. No operation
16.18. Thumb instructions
17. AC Characteristics
17.1. Processor timing diagrams
17.2. Processor timing parameters
18. Introduction to the VFP coprocessor
18.1. About the VFP11 coprocessor
18.2. Applications
18.3. Coprocessor interface
18.4. VFP11 coprocessor pipelines
18.4.1. FMAC pipeline
18.4.2. DS pipeline
18.4.3. LS pipeline
18.5. Modes of operation
18.5.1. Full-compliance mode
18.5.2. Flush-to-zero mode
18.5.3. Default NaN mode
18.5.4. RunFast mode
18.6. Short vector instructions
18.7. Parallel execution of instructions
18.8. VFP11 treatment of branch instructions
18.9. Writing optimal VFP11 code
18.10. VFP11 revision information
19. The VFP Register File
19.1. About the register file
19.2. Register file internal formats
19.2.1. Integer data format
19.2.2. Single-precision data format
19.2.3. Double-precision data format
19.3. Decoding the register file
19.4. Loading operands from ARM11 registers
19.5. Maintaining consistency in register precision
19.6. Data transfer between memory and VFP11 registers
19.7. Access to register banks in CDP operations
19.7.1. About register banks
19.7.2. Operations using register banks
20. VFP Programmer’s Model
20.1. About the programmer’s model
20.2. Compliance with the IEEE 754 standard
20.2.1. An IEEE 754 standard-compliant implementation
20.2.2. Complete implementation of the IEEE 754 standard
20.2.3. IEEE 754 standard implementation choices
20.3. ARMv5TE coprocessor extensions
20.3.1. FMDRR
20.3.2. FMRRD
20.3.3. FMSRR
20.3.4. FMRRS
20.4. VFP11 system registers
20.4.1. Floating-Point System ID Register, FPSID
20.4.2. Floating-Point Status and Control Register, FPSCR
20.4.3. Floating-point exception register, FPEXC
20.4.4. Instruction registers, FPINST and FPINST2
20.4.5. Media and VFP Feature Register 0
20.4.6. Media and VFP Feature Register 1
21. VFP Instruction Execution
21.1. About instruction execution
21.2. Serializing instructions
21.3. Interrupting the VFP11 coprocessor
21.4. Forwarding
21.5. Hazards
21.6. Operation of the scoreboards
21.6.1. Scoreboard operation when an instruction bounces
21.6.2. Single-precision source register locking
21.6.3. Single-precision source register clearing
21.6.4. Double-precision source register locking
21.6.5. Double-precision source register clearing
21.7. Data hazards in full-compliance mode
21.7.1. Status register RAW hazard example
21.7.2. Load multiple-CDP RAW hazard example
21.7.3. Load multiple-short vector CDP RAW hazard example
21.7.4. CDP-CDP RAW hazard example
21.7.5. Short vector CDP-load multiple WAR hazard example
21.8. Data hazards in RunFast mode
21.8.1. Short vector CDP-load multiple WAR hazard example
21.9. Resource hazards
21.9.1. Load multiple-load-CDP resource hazard example
21.9.2. Load multiple-short vector CDP resource hazard example
21.9.3. Short vector CDP-CDP resource hazard example
21.10. Parallel execution
21.11. Execution timing
22. VFP Exception Handling
22.1. About exception processing
22.2. Bounced instructions
22.2.1. Potential or actual exception that the VFP11 coprocessor cannot handle
22.2.2. Potential or actual exception with the exception enable bit set
22.3. Support code
22.3.1. Illegal instructions
22.4. Exception processing
22.4.1. Determination of the trigger instruction
22.4.2. Exception processing for CDP scalar instructions
22.4.3. Exception processing for CDP short vector instructions
22.4.4. Examples of exception detection for vector instructions
22.5. Input Subnormal exception
22.5.1. Exception enabled
22.5.2. Exception disabled
22.6. Invalid Operation exception
22.6.1. Exception enabled
22.6.2. Exception disabled
22.7. Division by Zero exception
22.7.1. Exception enabled
22.7.2. Exception disabled
22.8. Overflow exception
22.8.1. Exception enabled
22.8.2. Exception disabled
22.9. Underflow exception
22.9.1. Exception enabled
22.9.2. Exception disabled
22.10. Inexact exception
22.10.1. Exception enabled
22.10.2. Exception disabled
22.11. Input exceptions
22.12. Arithmetic exceptions
22.12.1. FADD and FSUB
22.12.2. FCMP, FCMPZ, FCMPE, and FCMPEZ
22.12.3. FMUL and FNMUL
22.12.4. FMAC, FMSC, FNMAC, and FNMSC
22.12.5. FDIV
22.12.6. FSQRT
22.12.7. FCPY, FABS, and FNEG
22.12.8. FCVTDS and FCVTSD
22.12.9. FUITO and FSITO
22.12.10. FTOUI, FTOUIZ, FTOSI, and FTOSIZ
A. Signal Descriptions
A.1. Global signals
A.2. Static configuration signals
A.3. TrustZone internal signals
A.4. Interrupt signals, including VIC interface
A.5. AXI interface signals
A.5.1. Instruction read port signals
A.5.2. Data port signals
A.5.3. Peripheral port signals
A.5.4. DMA port signals
A.6. Coprocessor interface signals
A.7. Debug interface signals, including JTAG
A.8. ETM interface signals
A.9. Test signals
B. Summary of ARM1136JF-S and ARM1176JZF-S Processor Differences
B.1. About the differences between the ARM1136JF-S and ARM1176JZF-S processors
B.2. Summary of differences
B.2.1. TrustZone
B.2.2. ARMv6k extensions support
B.2.3. Power management
B.2.4. SmartCache
B.2.5. CPU ID
B.2.6. Block transfer operations
B.2.7. Tightly-Coupled Memories
B.2.8. Fault Address Register
B.2.9. Fault Status Register
B.2.10. Prefetch Unit
B.2.11. System control coprocessor operations
B.2.12. DMA
B.2.13. Debug
B.2.14. Level two interface
B.2.15. Memory BIST
C. Revisions
Glossary

List of Figures

1. Key to timing diagram conventions
1.1. ARM1176JZF-S processor block diagram
1.2. ARM1176JZF-S pipeline stages
1.3. Typical operations in pipeline stages
1.4. Typical ALU operation
1.5. Typical multiply operation
1.6. Progression of an LDR/STR operation
1.7. Progression of an LDM/STM operation
1.8. Progression of an LDR that misses
2.1. Secure and Non-secure worlds
2.2. Memory in the Secure and Non-secure worlds
2.3. Memory partition in the Secure and Non-secure worlds
2.4. Big-endian addresses of bytes within words
2.5. Little-endian addresses of bytes within words
2.6. Register organization in ARM state
2.7. Processor core register set showing banked registers
2.8. Register organization in Thumb state
2.9. ARM state and Thumb state registers relationship
2.10. Program status register
2.11. LDREXB instruction
2.12. STREXB instructions
2.13. LDREXH instruction
2.14. STREXH instruction
2.15. LDREXD instruction
2.16. STREXD instruction
2.17. CLREX instruction
2.18. NOP-compatible hint instruction
3.1. System control and configuration registers
3.2. MMU control and configuration registers
3.3. Cache control and configuration registers
3.4. TCM control and configuration registers
3.5. Cache Master Valid Registers
3.6. DMA control and configuration registers
3.7. System performance monitor registers
3.8. System validation registers
3.9. CP15 MRC and MCR bit pattern
3.10. Main ID Register format
3.11. Cache Type Register format
3.12. TCM Status Register format
3.13. TLB Type Register format
3.14. Processor Feature Register 0 format
3.15. Processor Feature Register 1 format
3.16. Debug Feature Register 0 format
3.17. Memory Model Feature Register 0 format
3.18. Memory Model Feature Register 1 format
3.19. Memory Model Feature Register 2 format
3.20. Memory Model Feature Register 3 format
3.21. Instruction Set Attributes Register 0 format
3.22. Instruction Set Attributes Register 1 format
3.23. Instruction Set Attributes Register 2 format
3.24. Instruction Set Attributes Register 3 format
3.25. Instruction Set Attributes Register 4 format
3.26. Control Register format
3.27. Auxiliary Control Register format
3.28. Coprocessor Access Control Register format
3.29. Secure Configuration Register format
3.30. Secure Debug Enable Register format
3.31. Non-Secure Access Control Register format
3.32. Translation Table Base Register 0 format
3.33. Translation Table Base Register 1 format
3.34. Translation Table Base Control Register format
3.35. Domain Access Control Register format
3.36. Data Fault Status Register format
3.37. Instruction Fault Status Register format
3.38. Cache operations
3.39. Cache operations with MCRR instructions
3.40. c7 format for Set and Index
3.41. c7 format for MVA
3.42. Format of c7 for VA
3.43. Cache Dirty Status Register format
3.44. c7 format for Flush Branch Target Entry using MVA
3.45. PA Register format for successful translation
3.46. PA Register format for aborted translation
3.47. TLB Operations Register MVA and ASID format
3.48. TLB Operations Register ASID format
3.49. Instruction and data cache lockdown register formats
3.50. Data TCM Region Register format
3.51. Instruction TCM Region Register format
3.52. Data TCM Non-secure Control Access Register format
3.53. Instruction TCM Non-secure Control Access Register format
3.54. TCM Selection Register format
3.55. Cache Behavior Override Register format
3.56. TLB Lockdown Register format
3.57. Primary Region Remap Register format
3.58. Normal Memory Remap Register format
3.59. DMA identification and status registers format
3.60. DMA User Accessibility Register format
3.61. DMA Channel Number Register format
3.62. DMA Control Register format
3.63. DMA Channel Status Register format
3.64. DMA Context ID Register format
3.65. Secure or Non-secure Vector Base Address Register format
3.66. Monitor Vector Base Address Register format
3.67. Interrupt Status Register format
3.68. FCSE PID Register format
3.69. Address mapping with the FCSE PID Register
3.70. Context ID Register format
3.71. Peripheral Port Memory Remap Register format
3.72. Secure User and Non-secure Access Validation Control Register format
3.73. Performance Monitor Control Register format
3.74. System Validation Counter Register format for external debug request counter
3.75. System Validation Cache Size Mask Register format
3.76. TLB Lockdown Index Register format
3.77. TLB Lockdown VA Register format
3.78. TLB Lockdown PA Register format
3.79. TLB Lockdown Attributes Register format
4.1. Load unsigned byte
4.2. Load signed byte
4.3. Store byte
4.4. Load unsigned halfword, little-endian
4.5. Load unsigned halfword, big-endian
4.6. Load signed halfword, little-endian
4.7. Load signed halfword, big-endian
4.8. Store halfword, little-endian
4.9. Store halfword, big-endian
4.10. Load word, little-endian
4.11. Load word, big-endian
4.12. Store word, little-endian
4.13. Store word, big-endian
6.1. Memory ordering restrictions
6.2. Translation table managed TLB fault checking sequence part 1
6.3. Translation table managed TLB fault checking sequence part 2
6.4. Backwards-compatible first-level descriptor format
6.5. Backwards-compatible second-level descriptor format
6.6. Backwards-compatible section, supersection, and page translation
6.7. ARMv6 first-level descriptor formats with subpages disabled
6.8. ARMv6 second-level descriptor format
6.9. ARMv6 section, supersection, and page translation
6.10. Creating a first-level descriptor address
6.11. Translation for a 1MB section, ARMv6 format
6.12. Translation for a 1MB section, backwards-compatible format
6.13. Generating a second-level page table address
6.14. Large page table walk, ARMv6 format
6.15. Large page table walk, backwards-compatible format
6.16. 4KB small page or 1KB small subpage translations, backwards-compatible format
6.17. 4KB extended small page translations, ARMv6 format
6.18. 4KB extended small page or 1KB extended small subpage translations, backwards-compatible format
7.1. Level one cache block diagram
8.1. Level two interconnect interfaces
8.2. Channel architecture of reads
8.3. Channel architecture of writes
8.4. Swizzling of data and strobes in BE-32 big-endian configuration
9.1. Processor clocks with no IEM
9.2. Read latency with no IEM
9.3. Processor clocks with IEM
9.4. Processor synchronization with IEM
9.5. Read latency with IEM
9.6. Power-on reset
10.1. IEM structure
11.1. Core and coprocessor pipelines
11.2. Coprocessor pipeline and queues
11.3. Coprocessor pipeline
11.4. Token queue buffers
11.5. Queue reading and writing
11.6. Queue flushing
11.7. Instruction queue
11.8. Coprocessor data transfer
11.9. Instruction iteration for loads
11.10. Load data buffering
12.1. Connection of a VIC to the processor
12.2. VIC port timing example
12.3. Interrupt entry sequence
13.1. Typical debug system
13.2. Debug ID Register format
13.3. Debug Status and Control Register format
13.4. DTR format
13.5. Vector Catch Register format
13.6. Breakpoint Control Registers, format
13.7. Watchpoint Control Registers, format
14.1. JTAG DBGTAP state machine diagram
14.2. RealView ICE clock synchronization
14.3. Bypass register bit order
14.4. Device ID code register bit order
14.5. Instruction register bit order
14.6. Scan chain select register bit order
14.7. Scan chain 0 bit order
14.8. Scan chain 1 bit order
14.9. Scan chain 4 bit order
14.10. Scan chain 5 bit order, EXTEST selected
14.11. Scan chain 5 bit order, INTEST selected
14.12. Scan chain 6 bit order
14.13. Scan chain 7 bit order
14.14. Behavior of the ITRsel IR instruction
15.1. ETMCPADDRESS format
18.1. FMAC pipeline
18.2. DS pipeline
18.3. LS pipeline
19.1. Single-precision data format
19.2. Double-precision data format
19.3. Register file access
19.4. Register banks
20.1. FMDRR instruction format
20.2. FMRRD instruction format
20.3. FMSRR instruction format
20.4. FMRRS instruction format
20.5. Floating-Point System ID Register
20.6. Floating-Point Status and Control Register
20.7. Floating-Point Exception Register
20.8. Media and VFP Feature Register 0 format
20.9. Media and VFP Feature Register 1 format

List of Tables

1.1. TCM configurations
1.2. Double-precision VFP operations
1.3. Flush-to-zero mode
1.4. Configurable options
1.5. ARM1176JZF-S processor default configurations
1.6. Key to instruction set tables
1.7. ARM instruction set summary
1.8. Addressing mode 2
1.9. Addressing mode 2P, post-indexed only
1.10. Addressing mode 3
1.11. Addressing mode 4
1.12. Addressing mode 5
1.13. Operand2
1.14. Fields
1.15. Condition codes
1.16. Thumb instruction set summary
2.1. Write access behavior for system control processor registers
2.2. Secure Monitor bus signals
2.3. Address types in the processor system
2.4. Mode structure
2.5. Register mode identifiers
2.6. GE[3:0] settings
2.7. PSR mode bit values
2.8. Exception entry and exit
2.9. Exception priorities
3.1. System control coprocessor register functions
3.2. Summary of CP15 registers and operations
3.3. Summary of CP15 MCRR operations
3.4. Main ID Register bit functions
3.5. Results of access to the Main ID Register
3.6. Cache Type Register bit functions
3.7. Results of access to the Cache Type Register
3.8. Example Cache Type Register format
3.9. TCM Status Register bit functions
3.10. TLB Type Register bit functions
3.11. Results of access to the TLB Type Register
3.12. Processor Feature Register 0 bit functions
3.13. Results of access to the Processor Feature Register 0
3.14. Processor Feature Register 1 bit functions
3.15. Results of access to the Processor Feature Register 1
3.16. Debug Feature Register 0 bit functions
3.17. Results of access to the Debug Feature Register 0
3.18. Auxiliary Feature Register 0 bit functions
3.19. Results of access to the Auxiliary Feature Register 0
3.20. Memory Model Feature Register 0 bit functions
3.21. Results of access to the Memory Model Feature Register 0
3.22. Memory Model Feature Register 1 bit functions
3.23. Results of access to the Memory Model Feature Register 1
3.24. Memory Model Feature Register 2 bit functions
3.25. Results of access to the Memory Model Feature Register 2
3.26. Memory Model Feature Register 3 bit functions
3.27. Results of access to the Memory Model Feature Register 3
3.28. Instruction Set Attributes Register 0 bit functions
3.29. Results of access to the Instruction Set Attributes Register 0
3.30. Instruction Set Attributes Register 1 bit functions
3.31. Results of access to the Instruction Set Attributes Register 1
3.32. Instruction Set Attributes Register 2 bit functions
3.33. Results of access to the Instruction Set Attributes Register 2
3.34. Instruction Set Attributes Register 3 bit functions
3.35. Results of access to the Instruction Set Attributes Register 3
3.36. Instruction Set Attributes Register 4 bit functions
3.37. Results of access to the Instruction Set Attributes Register 4
3.38. Results of access to the Instruction Set Attributes Register 5
3.39. Control Register bit functions
3.40. Results of access to the Control Register
3.41. Resultant B bit, U bit, and EE bit values
3.42. Auxiliary Control Register bit functions
3.43. Results of access to the Auxiliary Control Register
3.44. Coprocessor Access Control Register bit functions
3.45. Results of access to the Coprocessor Access Control Register
3.46. Secure Configuration Register bit functions
3.47. Operation of the FW and FIQ bits
3.48. Operation of the AW and EA bits
3.49. Secure Debug Enable Register bit functions
3.50. Results of access to the Coprocessor Access Control Register
3.51. Non-Secure Access Control Register bit functions
3.52. Results of access to the Auxiliary Control Register
3.53. Translation Table Base Register 0 bit functions
3.54. Results of access to the Translation Table Base Register 0
3.55. Translation Table Base Register 1 bit functions
3.56. Results of access to the Translation Table Base Register 1
3.57. Translation Table Base Control Register bit functions
3.58. Results of access to the Translation Table Base Control Register
3.59. Domain Access Control Register bit functions
3.60. Results of access to the Domain Access Control Register
3.61. Data Fault Status Register bit functions
3.62. Results of access to the Data Fault Status Register
3.63. Instruction Fault Status Register bit functions
3.64. Results of access to the Instruction Fault Status Register
3.65. Results of access to the Fault Address Register
3.66. Results of access to the Instruction Fault Address Register
3.67. Functional bits of c7 for Set and Index
3.68. Cache size and S parameter dependency
3.69. Functional bits of c7 for MVA
3.70. Functional bits of c7 for VA format
3.71. Cache operations for entire cache
3.72. Cache operations for single lines
3.73. Cache operations for address ranges
3.74. Cache Dirty Status Register bit functions
3.75. Cache operations flush functions
3.76. Flush Branch Target Entry using MVA bit functions
3.77. PA Register for successful translation bit functions
3.78. PA Register for unsuccessful translation bit functions
3.79. Results of access to the Data Synchronization Barrier operation
3.80. Results of access to the Data Memory Barrier operation
3.81. Results of access to the Wait For Interrupt operation
3.82. Results of access to the TLB Operations Register
3.83. Instruction and data cache lockdown register bit functions
3.84. Results of access to the Instruction and Data Cache Lockdown Register
3.85. Data TCM Region Register bit functions
3.86. Results of access to the Data TCM Region Register
3.87. Instruction TCM Region Register bit functions
3.88. Results of access to the Instruction TCM Region Register
3.89. Data TCM Non-secure Control Access Register bit functions
3.90. Effects of NS items for data TCM operation
3.91. Instruction TCM Non-secure Control Access Register bit functions
3.92. Effects of NS items for instruction TCM operation
3.93. TCM Selection Register bit functions
3.94. Results of access to the TCM Selection Register
3.95. Cache Behavior Override Register bit functions
3.96. Results of access to the Cache Behavior Override Register
3.97. TLB Lockdown Register bit functions
3.98. Results of access to the TLB Lockdown Register
3.99. Primary Region Remap Register bit functions
3.100. Encoding for the remapping of the primary memory type
3.101. Normal Memory Remap Register bit functions
3.102. Remap encoding for Inner or Outer cacheable attributes
3.103. Results of access to the memory region remap registers
3.104. DMA identification and status register bit functions
3.105. DMA Identification and Status Register functions
3.106. Results of access to the DMA identification and status registers
3.107. DMA User Accessibility Register bit functions
3.108. Results of access to the DMA User Accessibility Register
3.109. DMA Channel Number Register bit functions
3.110. Results of access to the DMA Channel Number Register
3.111. Results of access to the DMA enable registers
3.112. DMA Control Register bit functions
3.113. Results of access to the DMA Control Register
3.114. Results of access to the DMA Internal Start Address Register
3.115. Results of access to the DMA External Start Address Register
3.116. Results of access to the DMA Internal End Address Register
3.117. DMA Channel Status Register bit functions
3.118. Results of access to the DMA Channel Status Register
3.119. DMA Context ID Register bit functions
3.120. Results of access to the DMA Context ID Register
3.121. Secure or Non-secure Vector Base Address Register bit functions
3.122. Results of access to the Secure or Non-secure Vector Base Address Register
3.123. Monitor Vector Base Address Register bit functions
3.124. Results of access to the Monitor Vector Base Address Register
3.125. Interrupt Status Register bit functions
3.126. Results of access to the Interrupt Status Register
3.127. FCSE PID Register bit functions
3.128. Results of access to the FCSE PID Register
3.129. Context ID Register bit functions
3.130. Results of access to the Context ID Register
3.131. Results of access to the thread and process ID registers
3.132. Peripheral Port Memory Remap Register bit functions
3.133. Results of access to the Peripheral Port Remap Register
3.134. Secure User and Non-secure Access Validation Control Register bit functions
3.135. Results of access to the Secure User and Non-secure Access Validation Control Register
3.136. Performance Monitor Control Register bit functions
3.137. Performance monitoring events
3.138. Results of access to the Performance Monitor Control Register
3.139. Results of access to the Cycle Counter Register
3.140. Results of access to the Count Register 0
3.141. Results of access to the Count Register 1
3.142. System validation counter register operations
3.143. Results of access to the System Validation Counter Register
3.144. System Validation Operations Register functions
3.145. Results of access to the System Validation Operations Register
3.146. System Validation Cache Size Mask Register bit functions
3.147. Results of access to the System Validation Cache Size Mask Register
3.148. TLB Lockdown Index Register bit functions
3.149. TLB Lockdown VA Register bit functions
3.150. TLB Lockdown PA Register bit functions
3.151. Access permissions APX and AP bit fields encoding
3.152. TLB Lockdown Attributes Register bit functions
3.153. Results of access to the TLB lockdown access registers
4.1. Unaligned access handling
4.2. Memory access types
4.3. Unalignment fault occurrence when access behavior is architecturally unpredictable
4.4. Legacy endianness using CP15 c1
4.5. Mixed-endian configuration
4.6. B bit, U bit, and EE bit settings
6.1. Access permission bit encoding
6.2. TEX field, and C and B bit encodings used in page table formats
6.3. Cache policy bits
6.4. Inner and Outer cache policy implementation options
6.5. Effect of remapping memory with TEX remap = 1
6.6. Values that remap the shareable attribute
6.7. Primary region type encoding
6.8. Inner and outer region remap encoding
6.9. Memory attributes
6.10. Memory region backwards compatibility
6.11. Fault Status Register encoding
6.12. Summary of aborts
6.13. Translation table size
6.14. Access types from first-level descriptor bit values
6.15. Access types from second-level descriptor bit values
6.16. CP15 register functions
6.17. CP14 register functions
7.1. TCM configurations
7.2. Access to Non-secure TCM
7.3. Access to Secure TCM
7.4. Summary of data accesses to TCM and caches
7.5. Summary of instruction accesses to TCM and caches
8.1. AXI parameters for the level 2 interconnect interfaces
8.2. AxLEN[3:0] encoding
8.3. AxSIZE[2:0] encoding
8.4. AxBURST[1:0] encoding
8.5. AxLOCK[1:0] encoding
8.6. AxCACHE[3:0] encoding
8.7. AxPROT[2:0] encoding
8.8. AxSIDEBAND[4:1] encoding
8.9. ARSIDEBANDI[4:1] encoding
8.10. AXI signals for Cacheable fetches
8.11. AXI signals for Noncacheable fetches
8.12. Linefill behavior on the AXI interface
8.13. Noncacheable LDRB
8.14. Noncacheable LDRH
8.15. Noncacheable LDR or LDM1
8.16. Noncacheable LDRD or LDM2
8.17. Noncacheable LDRD or LDM2 from word 7
8.18. Noncacheable LDM3, Strongly Ordered or Device memory
8.19. Noncacheable LDM3, Noncacheable memory or cache disabled
8.20. Noncacheable LDM3 from word 6, or 7
8.21. Noncacheable LDM4, Strongly Ordered or Device memory
8.22. Noncacheable LDM4, Noncacheable memory or cache disabled
8.23. Noncacheable LDM4 from word 5, 6, or 7
8.24. Noncacheable LDM5, Strongly Ordered or Device memory
8.25. Noncacheable LDM5, Noncacheable memory or cache disabled
8.26. Noncacheable LDM5 from word 4, 5, 6, or 7
8.27. Noncacheable LDM6, Strongly Ordered or Device memory
8.28. Noncacheable LDM6, Noncacheable memory or cache disabled
8.29. Noncacheable LDM6 from word 3, 4, 5, 6, or 7
8.30. Noncacheable LDM7, Strongly Ordered or Device memory
8.31. Noncacheable LDM7, Noncacheable memory or cache disabled
8.32. Noncacheable LDM7 from word 2, 3, 4, 5, 6, or 7
8.33. Noncacheable LDM8 from word 0
8.34. Noncacheable LDM8 from word 1, 2, 3, 4, 5, 6, or 7
8.35. Noncacheable LDM9
8.36. Noncacheable LDM10
8.37. Noncacheable LDM11
8.38. Noncacheable LDM12
8.39. Noncacheable LDM13
8.40. Noncacheable LDM14
8.41. Noncacheable LDM15
8.42. Noncacheable LDM16
8.43. Half-line Write-Back
8.44. Full-line Write-Back
8.45. Cacheable Write-Through or Noncacheable STRB
8.46. Cacheable Write-Through or Noncacheable STRH
8.47. Cacheable Write-Through or Noncacheable STR or STM1
8.48. Cacheable Write-Through or Noncacheable STRD or STM2 to words 0, 1, 2, 3, 4, 5, or 6
8.49. Cacheable Write-Through or Noncacheable STM2 to word 7
8.50. Cacheable Write-Through or Noncacheable STM3 to words 0, 1, 2, 3, 4, or 5
8.51. Cacheable Write-Through or Noncacheable STM3 to words 6 or 7
8.52. Cacheable Write-Through or Noncacheable STM4 to word 0, 1, 2, 3, or 4
8.53. Cacheable Write-Through or Noncacheable STM4 to word 5, 6, or 7
8.54. Cacheable Write-Through or Noncacheable STM5 to word 0, 1, 2, or 3
8.55. Cacheable Write-Through or Noncacheable STM5 to word 4, 5, 6, or 7
8.56. Cacheable Write-Through or Noncacheable STM6 to word 0, 1, or 2
8.57. Cacheable Write-Through or Noncacheable STM6 to word 3, 4, 5, 6, or 7
8.58. Cacheable Write-Through or Noncacheable STM7 to word 0 or 1
8.59. Cacheable Write-Through or Noncacheable STM7 to word 2, 3, 4, 5, 6 or 7
8.60. Cacheable Write-Through or Noncacheable STM8 to word 0
8.61. Cacheable Write-Through or Noncacheable STM8 to word 1, 2, 3, 4, 5, 6, or 7
8.62. Cacheable Write-Through or Noncacheable STM9
8.63. Cacheable Write-Through or Noncacheable STM10
8.64. Cacheable Write-Through or Noncacheable STM11
8.65. Cacheable Write-Through or Noncacheable STM12
8.66. Cacheable Write-Through or Noncacheable STM13
8.67. Cacheable Write-Through or Noncacheable STM14
8.68. Cacheable Write-Through or Noncacheable STM15
8.69. Cacheable Write-Through or Noncacheable STM16
8.70. Example Peripheral Interface reads and writes
9.1. Reset modes
11.1. Coprocessor instructions
11.2. Coprocessor control signals
11.3. Pipeline stage update
11.4. Addressing of queue buffers
11.5. Retirement conditions
12.1. VIC port signals
13.1. Terms used in register descriptions
13.2. CP14 debug register map
13.3. Debug ID Register bit field definition
13.4. Debug Status and Control Register bit field definitions
13.5. Data Transfer Register bit field definitions
13.6. Vector Catch Register bit field definitions
13.7. Summary of debug entry and exception conditions
13.8. Processor breakpoint and watchpoint registers
13.9. Breakpoint Value Registers, bit field definition
13.10. Processor Breakpoint Control Registers
13.11. Breakpoint Control Registers, bit field definitions
13.12. Meaning of BCR[22:20] bits
13.13. Processor Watchpoint Value Registers
13.14. Watchpoint Value Registers, bit field definitions
13.15. Processor Watchpoint Control Registers
13.16. Watchpoint Control Registers, bit field definitions
13.17. Debug State Cache Control Register bit functions
13.18. Debug State MMU Control Register bit functions
13.19. CP14 debug instructions
13.20. Debug instruction execution
13.21. Secure debug behavior
13.22. Behavior of the processor on debug events
13.23. Setting of CP15 registers on debug events
13.24. Values in the link register after exceptions
13.25. Read PC value after Debug state entry
13.26. Example memory operation sequence
14.1. Supported public instructions
14.2. Scan chain 7 register map
15.1. Instruction interface signals
15.2. ETMIACTL[17:0]
15.3. ETMIASECCTL[1:0]
15.4. Data address interface signals
15.5. ETMDACTL[17:0]
15.6. Data value interface signals
15.7. ETMDDCTL[3:0]
15.8. ETMPADV[2:0]
15.9. Coprocessor interface signals
15.10. ETMCPSECCTL[1:0] format
15.11. Other connections
16.1. Pipeline stages
16.2. Definition of cycle timing terms
16.3. Register interlock examples
16.4. Data Processing Instruction cycle timing behavior if destination is not PC
16.5. Data Processing Instruction cycle timing behavior if destination is the PC
16.6. QADD, QDADD, QSUB, and QDSUB instruction cycle timing behavior
16.7. ARMv6 media data-processing instructions cycle timing behavior
16.8. ARMv6 sum of absolute differences instruction timing behavior
16.9. Example interlocks
16.10. Example multiply instruction cycle timing behavior
16.11. Branch instruction cycle timing behavior
16.12. Processor state updating instructions cycle timing behavior
16.13. Cycle timing behavior for stores and loads, other than loads to the PC
16.14. Cycle timing behavior for loads to the PC
16.15. <addr_md_1cycle> and <addr_md_2cycle> LDR example instruction explanation
16.16. Load and Store Double instructions cycle timing behavior
16.17. <addr_md_1cycle> and <addr_md_2cycle> LDRD example instruction explanation
16.18. Cycle timing behavior of Load and Store Multiples, other than load multiples including the PC
16.19. Cycle timing behavior of Load Multiples, where the PC is in the register list
16.20. RFE and SRS instructions cycle timing behavior
16.21. Synchronization Instructions cycle timing behavior
16.22. Coprocessor Instructions cycle timing behavior
16.23. SVC, BKPT, undefined, prefetch aborted instructions cycle timing behavior
17.1. Global signals
17.2. AXI signals
17.3. Coprocessor signals
17.4. ETM interface signals
17.5. Interrupt signals
17.6. Debug interface signals
17.7. Test signals
17.8. Static configuration signals
17.9. TrustZone internal signals
19.1. VFP11 MCR instructions
19.2. VFP11 MRC instructions
19.3. VFP11 MCRR instructions
19.4. VFP11 MRRC instructions
19.5. Single-precision data memory images and byte addresses
19.6. Double-precision data memory images and byte addresses
19.7. Single-precision three-operand register usage
19.8. Single-precision two-operand register usage
19.9. Double-precision three-operand register usage
19.10. Double-precision two-operand register usage
20.1. Default NaN values
20.2. QNaN and SNaN handling
20.3. VFP11 system registers
20.4. Accessing VFP11 system registers
20.5. FPSID bit fields
20.6. Encoding of the Floating-Point Status and Control Register
20.7. Vector length and stride combinations
20.8. Encoding of the Floating-Point Exception Register
20.9. Media and VFP Feature Register 0 bit functions
20.10. Media and VFP Feature Register 1 bit functions
21.1. Single-precision source register locking
21.2. Single-precision source register clearing
21.3. Double-precision source register locking
21.4. Double-precision source register clearing for one-cycle instructions
21.5. Double-precision source register clearing for two-cycle instructions
21.6. FCMPS-FMSTAT RAW hazard
21.7. FLDM-FADDS RAW hazard
21.8. FLDM-short vector FADDS RAW hazard
21.9. FMULS-FADDS RAW hazard
21.10. Short vector FMULS-FLDMS WAR hazard
21.11. Short vector FMULS-FLDMS WAR hazard in RunFast mode
21.12. FLDM-FLDS-FADDS resource hazard
21.13. FLDM-short vector FMULS resource hazard
21.14. Short vector FDIVS-FADDS resource hazard
21.15. Parallel execution in all three pipelines
21.16. Throughput and latency cycle counts for VFP11 instructions
22.1. Exceptional short vector FMULD followed by load/store instructions
22.2. Exceptional short vector FADDS with a FADDS in the pretrigger slot
22.3. Exceptional short vector FADDD with an FMACS trigger instruction
22.4. Possible Invalid Operation exceptions
22.5. Default results for invalid conversion inputs
22.6. Rounding mode overflow results
22.7. LSA and USA determination
22.8. FADD family bounce thresholds
22.9. FMUL family bounce thresholds
22.10. FDIV bounce thresholds
22.11. FCVTSD bounce thresholds
22.12. Single-precision float-to-integer bounce thresholds and stored results
22.13. Double-precision float-to-integer bounce thresholds and stored results
A.1. Global signals
A.2. Static configuration signals
A.3. TrustZone internal signals
A.4. Interrupt signals
A.5. Port signal name suffixes
A.6. Instruction read port AXI signal implementation
A.7. Data port AXI signal implementation
A.8. Peripheral port AXI signal implementation
A.9. DMA port signals
A.10. Core to coprocessor signals
A.11. Coprocessor to core signals
A.12. Debug interface signals
A.13. ETM interface signals
A.14. Test signals
B.1. TCM for ARM1176JZF-S processors
B.2. CP15 c15 features common to ARM1136JF-S and ARM1176JZF-S processors
B.3. CP15 c15 only found in ARM1136JF-S processors
C.1. Differences between issue G and issue H

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Figure 14.1 reprinted with permission from IEEE Std. 1149.1-2001, IEEE Standard Test Access Port and Boundary-Scan Architecture by IEEE Std. The IEEE disclaims any responsibility or liability resulting from the placement and use in the described manner.

Some material in this document is based on IEEE Standard for Binary Floating-Point Arithmetic, ANSI/IEEE Std 754-1985. The IEEE disclaims any responsibility or liability resulting from the placement and use in the described manner

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Revision History
Revision A19 July 2004First release.
Revision B18 April 2005Minor corrections and enhancements.
Revision C29 June 2005r0p1 changes, addition of CPUCLAMPFigure 10-1 updated.Section 10.4.3 updated.Table 23-1 updated.Minor corrections and enhancements.
Revision D22 March 2006Update for r0p2. Minor corrections and enhancements.
Revision E19 July 2006Patch update for r0p4.
Revision F19 April 2007Update for r0p6 release. Minor corrections and enhancements.
Revision G15 February 2008Update for r0p7 release. Minor corrections and enhancements.
Revision H27 November 2009Update for r0p7 maintenance release. Minor corrections and enhancements.
Copyright © 2004-2009 ARM Limited. All rights reserved.ARM DDI 0301H
Non-Confidential