ARM1176JZF-S Technical Reference Manual: 6.10. Fault status and address

6.10. Fault status and address

Table 6.11 lists the encodings for the Fault Status Register.

Table 6.11. Fault Status Register encoding

Priority	Sources		FSR[10,3:0]	Domain	FSR[12]
Highest	Alignment		b00001	Invalid	SBZ
	TLB miss		b00000	Invalid	SBZ
	Instruction cache maintenance^[a] operation fault		b00100	Invalid	SBZ
	External abort on translation	first-level	b01100	Invalid	SLVERR !DECERR
		second-level	b01110	Valid	SLVERR !DECERR
	Translation	Section	b00101	Invalid	SBZ
		Page	b00111	Valid	SBZ
	Access Bit Fault, Force AP only	Section	b00011	Valid	SBZ
		Page	b00110	Valid	SBZ
	Domain	Section	b01001	Valid	SBZ
		Page	b01011	Valid	SBZ
	Permission	Section	b01101	Valid	SBZ
		Page	b01111	Valid	SBZ
	Precise external abort		b01000	Valid	SLVERR !DECERR
	Imprecise external abort		b10110	Invalid	SLVERR !DECERR
	Parity error exception, not supported		b11000	Invalid	SBZ
Lowest	Instruction debug event		b00010	Valid	SBZ
^[a]These aborts cannot be signaled with the IFSR because they do not occur on the instruction side.

Note

All other Fault Status encodings are reserved.

If a translation abort occurs during a Data Cache maintenance operation by virtual address, then a Data Abort is taken and the DFSR indicates the reason. The FAR indicates the faulting address, and the IFAR indicates the address of the instruction causing the abort.

If a translation abort occurs during an Instruction Cache maintenance operation by virtual address, then a Data Abort is taken, and an Instruction Cache Maintenance Operation Fault is indicated in the DFSR. The IFSR indicates the reason. The FAR indicates the faulting address, and the IFAR indicates the address of the instruction causing the abort.

Domain and fault address information is only available for data accesses. For instruction aborts R14 must be used to determine the faulting address. You can determine the domain information by performing a TLB lookup for the faulting address and extracting the domain field.

Table 6.12 lists a summary of the abort vector that is taken, and the Fault Status and Fault Address Registers that are updated for each abort type.

Table 6.12. Summary of aborts

Abort type	Abort taken	Precise?	Register updated?
Abort type	Abort taken	Precise?	IFSR	IFAR	DFSR	FAR	WFAR
Instruction MMU fault	Prefetch Abort	Yes	Yes	Yes	No	No	No
Instruction debug abort	Prefetch Abort	Yes	Yes	No	No	No	No
Instruction external abort on translation	Prefetch Abort	Yes^[a]	Yes^a	Yes	No	No	No
Instruction external abort	Prefetch Abort	Yes^a	Yes^a	Yes	No	No	No
Instruction cache maintenance operation	Data Abort	Yes	Yes	No	Yes	Yes	No
Data MMU fault	Data Abort	Yes	No	No	Yes	Yes	No
Data debug abort	Data Abort	No	No	No	Yes	Yes	Yes
Data external abort on translation	Data Abort	Yes^a	No	No	Yes^a	Yes^a	No^a
Data external abort	Data Abort	No^[b]	No	No	Yes^a	Yes	No
Data cache maintenance operation	Data Abort	Yes	No	No	Yes	Yes	No
^[a]When the EA bit is set, the updated FSR or FAR is always Secure. ^[b]Data Aborts can be precise, see External aborts for more details.

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