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Each TLB entry has an associated set of memory region attributes. These control:
accesses to the caches
how the write buffer is used
if the memory region is shareable
if the targeted memory is Secure or not.
| Copyright © 2004-2009 ARM Limited. All rights reserved. | ARM DDI 0301H |
| Non-Confidential | |
| PDF version | |
| Home > Memory Management Unit > Memory region attributes |