ARM1176JZF-S Technical Reference Manual: 3.2.10. c1, Secure Configuration Register

3.2.10. c1, Secure Configuration Register

The purpose of the Secure Configuration Register is to define:

the current world as Secure or Non-secure
the world in which the core executes exceptions
the ability to modify the A and I bits in the CPSR in the Non-secure world.

The Secure Configuration Register is:

in CP15 c1
a 32 bit read/write register
accessible in Secure privileged modes only.

Figure 3.29 shows the arrangement of bits in the register.

Figure 3.29. Secure Configuration Register format

Table 3.46 lists how the bit values correspond with the Secure Configuration Register functions.

Table 3.46. Secure Configuration Register bit functions

Bits	Field name	Function
[31:7]	-	UNP/SBZ.
[6]	nET	The Early Termination bit is not implemented in ARM1176JZF-S processors. UNP/SBZ.
[5]	AW	Determines if the A bit in the CPSR can be modified when in the Non-secure world: 0 = Disable modification of the A bit in the CPSR in the Non-secure world, reset value 1 = Enable modification of the A bit in the CPSR in the Non-secure world.
[4]	FW	Determines if the F bit in the CPSR can be modified when in the Non-secure world: 0 = Disable modification of the F bit in the CPSR in the Non-secure world, reset value 1 = Enable modification of the F bit in the CPSR in the Non-secure world.
[3]	EA	Determines External Abort behavior for Secure and Non-secure worlds: 0 = Branch to abort mode on an External Abort exception, reset value 1 = Branch to Secure Monitor mode on an External Abort exception.
[2]	FIQ	Determines FIQ behavior for Secure and Non-secure worlds: 0 = Branch to FIQ mode on an FIQ exception, reset value 1 = Branch to Secure Monitor mode on an FIQ exception.
[1]	IRQ	Determines IRQ behavior for Secure and Non-secure worlds: 0 = Branch to IRQ mode on an IRQ exception, reset value 1 = Branch to Secure Monitor mode on an IRQ exception.
[0]	NS bit	Defines the world for the processor: 0 = Secure, reset value 1 = Non-secure.

Note

When the core runs in Secure Monitor mode the state is considered Secure regardless of the state of the NS bit. However, Monitor mode code can access nonsecure banked copies of registers if the NS bit is set to 1. See the ARM Architecture Reference Manual for information on the effect of the Security Extensions on the CP15 registers.

The permutations of the bits in the Secure Configuration Register have certain security implications. Table 3.47 lists the results for combinations of the FW and FIQ bits.

Table 3.47. Operation of the FW and FIQ bits

FW	FIQ	Function
1	0	FIQs handled locally.
0	1	FIQs can be configured to give deterministic Secure interrupts.
1	1	Non-secure world able to make denial of service attack, avoid use of this function.
0	0	Avoid because the core might enter an infinite loop for Non-secure FIQ.

Table 3.48 lists the results for combinations of the AW and EA bits.

Table 3.48. Operation of the AW and EA bits

AW	EA	Function
1	0	Aborts handled locally.
0	1	All external aborts trapped to Secure Monitor.
1	1	All external imprecise data aborts trapped to Secure Monitor but the Non-secure world can hide Secure aborts from the Secure Monitor, avoid use of this function.
0	0	Avoid because the core can unexpectedly enter an abort mode in the Non-secure world.

For more details on the use of Secure Monitor mode, see The NS bit and Secure Monitor mode.

To use the Secure Configuration Register read or write CP15 with:

Opcode_1 set to 0
CRn set to c1
CRm set to c1
Opcode_2 set to 0.

For example:

MRC p15, 0, <Rd>, c1, c1, 0    ; Read Secure Configuration Register data

MCR p15, 0, <Rd>, c1, c1, 0    ; Write Secure Configuration Register data

An attempt to access the Secure Configuration Register from any state other than Secure privileged results in an Undefined exception.

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