ARM1176JZF-S Technical Reference Manual: 3.2.6. c0, CPUID registers

3.2.6. c0, CPUID registers

The section describes the CPUIID registers:

Note

The CPUID registers are sometimes described as the Core Feature ID registers.

c0, Processor Feature Register 0

The purpose of the Processor Feature Register 0 is to provide information about the execution state support and programmer’s model for the processor.

Processor Feature Register 0 is:

in CP15 c0
a 32-bit read-only register common to the Secure and Non-secure worlds
accessible in privileged modes only.

Table 3.12 lists how the bit values correspond with the Processor Feature Register 0 functions.

Figure 3.14 shows the bit arrangement for Processor Feature Register 0.

Figure 3.14. Processor Feature Register 0 format

Table 3.12. Processor Feature Register 0 bit functions

Bits	Field name	Function
[31:28]	-	Reserved. RAZ.
[27:24]	-	Reserved. RAZ.
[23:20]	-	Reserved. RAZ.
[19:16]	-	Reserved. RAZ.
[15:12]	State3	Indicates support for Thumb-2™ execution environment. `0x0`, ARM1176JZF-S processors do not support Thumb-2.
[11:8]	State2	Indicates support for Java extension interface. `0x1`, ARM1176JZF-S processors support Java.
[7:4]	State1	Indicates type of Thumb encoding that the processor supports. `0x1`, ARM1176JZF-S processors support Thumb-1 but do not support Thumb-2.
[3:0]	State0	Indicates support for 32-bit ARM instruction set. `0x1`, ARM1176JZF-S processors support 32-bit ARM instructions.

Table 3.13 lists the results of attempted access for each mode.

Table 3.13. Results of access to the Processor Feature Register 0

Secure Privileged		Non-secure Privileged		User
Read	Write	Read	Write	User
Data	Undefined exception	Data	Undefined exception	Undefined exception

To use the Processor Feature Register 0 read CP15 with:

Opcode_1 set to 0
CRn set to c0
CRm set to c1
Opcode_2 set to 0.

For example:

MRC p15, 0, <Rd>, c0, c1, 0 ;Read Processor Feature Register 0

c0, Processor Feature Register 1

The purpose of the Processor Feature Register 1 is to provide information about the execution state support and programmer’s model for the processor.

Processor Feature Register 1 is:

in CP15 c0
a 32-bit read-only register common to the Secure and Non-secure worlds
accessible in privileged modes only.

Figure 3.15 shows the bit arrangement for Processor Feature Register 1.

Figure 3.15. Processor Feature Register 1 format

Table 3.14 lists how the bit values correspond with the Processor Feature Register 1 functions.

Table 3.14. Processor Feature Register 1 bit functions

Bits	Field name	Function
[31:28]	-	Reserved. RAZ
[27:24]	-	Reserved. RAZ.
[23:20]	-	Reserved. RAZ.
[19:16]	-	Reserved. RAZ.
[15:12]	-	Reserved. RAZ.
[11:8]	Microcontroller programmer’s model	Indicates support for the ARM microcontroller programmer’s model. `0x0`, Not supported by ARM1176JZF-S processors.
[7:4]	Security extension	Indicates support for Security Extensions Architecture v1. `0x1`, ARM1176JZF-S processors support Security Extensions Architecture v1, TrustZone.
[3:0]	Programmer’s model	Indicates support for standard ARMv4 programmer’s model. `0x1`, ARM1176JZF-S processors support the ARMv4 model.

Table 3.15 lists the results of attempted access for each mode.

Table 3.15. Results of access to the Processor Feature Register 1

Secure Privileged		Non-secure Privileged		User
Read	Write	Read	Write	User
Data	Undefined exception	Data	Undefined exception	Undefined exception

To use the Processor Feature Register 1 read CP15 with:

Opcode_1 set to 0
CRn set to c0
CRm set to c1
Opcode_2 set to 1.

For example:

MRC p15, 0, <Rd>, c0, c1, 1 ;Read Processor Feature Register 1

c0, Debug Feature Register 0

The purpose of the Debug Feature Register 0 is to provide information about the debug system for the processor.

Debug Feature Register 0 is:

in CP15 c0
a 32-bit read-only register common to the Secure and Non-secure worlds
accessible in privileged modes only.

Figure 3.16 shows the bit arrangement for Debug Feature Register 0.

Figure 3.16. Debug Feature Register 0 format

Table 3.16 lists how the bit values correspond with the Debug Feature Register 0 functions.

Table 3.16. Debug Feature Register 0 bit functions

Bits	Field name	Function
[31:28]	-	Reserved. RAZ.
[27:24]	-	Reserved. RAZ.
[23:20]	-	Indicates the type of memory-mapped microcontroller debug model that the processor supports. `0x0`, ARM1176JZF-S processors do not support this debug model.
[19:16]	-	Indicates the type of memory-mapped Trace debug model that the processor supports. `0x0`, ARM1176JZF-S processors do not support this debug model.
[15:12]	-	Indicates the type of coprocessor-based Trace debug model that the processor supports. `0x0`, ARM1176JZF-S processors do not support this debug model.
[11:8]	-	Indicates the type of embedded processor debug model that the processor supports. `0x0`, ARM1176JZF-S processors do not support this debug model.
[7:4]	-	Indicates the type of Secure debug model that the processor supports. `0x3`, ARM1176JZF-S processors support the v6.1 Secure debug architecture based model.
[3:0]	-	Indicates the type of applications processor debug model that the processor supports. `0x3`, ARM1176JZF-S processors support the v6.1 debug model.

Table 3.17 lists the results of attempted access for each mode.

Table 3.17. Results of access to the Debug Feature Register 0

Secure Privileged		Non-secure Privileged		User
Read	Write	Read	Write	User
Data	Undefined exception	Data	Undefined exception	Undefined exception

To use the Debug Feature Register 0 read CP15 with:

Opcode_1 set to 0
CRn set to c0
CRm set to c1
Opcode_2 set to 2.

For example:

MRC p15, 0, <Rd>, c0, c1, 2 ;Read Debug Feature Register 0

c0, Auxiliary Feature Register 0

The purpose of the Auxiliary Feature Register 0 is to provide additional information about the features of the processor.

The Auxiliary Feature Register 0 is:

in CP15 c0
a 32-bit read-only register common to the Secure and Non-secure worlds
accessible in privileged modes only.

Table 3.18 lists how the bit values correspond with the Auxiliary Feature Register 0 functions.

Table 3.18. Auxiliary Feature Register 0 bit functions

Bits	Field name	Function
[31:16]	-	Reserved. RAZ.
[15:12]	-	Implementation Defined.
[11:8]	-	Implementation Defined.
[7:4]	-	Implementation Defined.
[3:0]	-	Implementation Defined.

The contents of the Auxiliary Feature Register 0 [31:16] are Reserved. The contents of the Auxiliary Feature Register 0 [15:0] are Implementation Defined. In the ARM1176JZF-S processor, the Auxiliary Feature Register 0 reads as 0x00000000.

Table 3.19 lists the results of attempted access for each mode.

Table 3.19. Results of access to the Auxiliary Feature Register 0

Secure Privileged		Non-secure Privileged		User
Read	Write	Read	Write	User
Data	Undefined exception	Data	Undefined exception	Undefined exception

To use the Auxiliary Feature Register 0 read CP15 with:

Opcode_1 set to 0
CRn set to c0
CRm set to c1
Opcode_2 set to 3.

For example:

MRC p15, 0, <Rd>, c0, c1, 3 ;Read Auxiliary Feature Register 0.

c0, Memory Model Feature Register 0

The purpose of the Memory Model Feature Register 0 is to provide information about the memory model, memory management, cache support, and TLB operations of the processor.

The Memory Model Feature Register 0 is:

in CP15 c0
a 32-bit read-only register common to the Secure and Non-secure worlds
accessible in privileged modes only.

Figure 3.17 shows the bit arrangement for Memory Model Feature Register 0.

Figure 3.17. Memory Model Feature Register 0 format

Table 3.20 lists how the bit values correspond with the Memory Model Feature Register 0 functions.

Table 3.20. Memory Model Feature Register 0 bit functions

Bits	Field name	Function
[31:28]	-	Reserved. RAZ.
[27:24]	-	Indicates support for FCSE. `0x1`, ARM1176JZF-S processors support FCSE.
[23:20]	-	Indicates support for the ARMv6 Auxiliary Control Register. `0x1`, ARM1176JZF-S processors support the Auxiliary Control Register.
[19:16]	-	Indicates support for TCM and associated DMA. `0x3`, ARM1176JZF-S processors support ARMv6 TCM and DMA.
[15:12]	-	Indicates support for cache coherency with DMA agent, shared memory. `0x0`, ARM1176JZF-S processors do not support this model.
[11:8]	-	Indicates support for cache coherency support with CPU agent, shared memory. `0x0`, ARM1176JZF-S processors do not support this model.
[7:4]	-	Indicates support for Protected Memory System Architecture (PMSA). `0x0`, ARM1176JZF-S processors do not support PMSA
[3:0]	-	Indicates support for Virtual Memory System Architecture (VMSA). `0x3`, ARM1176JZF-S processors support: VMSA v7 remapping and access flag.

Table 3.21 lists the results of attempted access for each mode.

Table 3.21. Results of access to the Memory Model Feature Register 0

Secure Privileged		Non-secure Privileged		User
Read	Write	Read	Write	User
Data	Undefined exception	Data	Undefined exception	Undefined exception

To use the Memory Model Feature Register 0 read CP15 with:

Opcode_1 set to 0
CRn set to c0
CRm set to c1
Opcode_2 set to 4.

For example:

MRC p15, 0, <Rd>, c0, c1, 4 ;Read Memory Model Feature Register 0.

c0, Memory Model Feature Register 1

The purpose of the Memory Model Feature Register 1 is to provide information about the memory model, memory management, cache support, and TLB operations of the processor.

The Memory Model Feature Register 1 is:

in CP15 c0
a 32-bit read-only register common to the Secure and Non-secure worlds
accessible in privileged modes only.

Figure 3.18 shows the bit arrangement for Memory Model Feature Register 1.

Figure 3.18. Memory Model Feature Register 1 format

Table 3.22 lists how the bit values correspond with the Memory Model Feature Register 1 functions.

Table 3.22. Memory Model Feature Register 1 bit functions

Bits	Field name	Function
[31:28]	-	Indicates support for branch target buffer. `0x1`, ARM1176JZF-S processors require flushing of branch predictor on VA change.
[27:24]	-	Indicates support for test and clean operations on data cache, Harvard or unified architecture. `0x0`, no support in ARM1176JZF-S processors.
[23:20]	-	Indicates support for level one cache, all maintenance operations, unified architecture. `0x0`, no support in ARM1176JZF-S processors.
[19:16]	-	Indicates support for level one cache, all maintenance operations, Harvard architecture. `0x3`, ARM1176JZF-S processors support: invalidate instruction cache including branch prediction invalidate data cache invalidate instruction and data cache including branch prediction clean data cache, recursive model using cache dirty status bit clean and invalidate data cache, recursive model using cache dirty status bit.
[15:12]	-	Indicates support for level one cache line maintenance operations by Set/Way, unified architecture. `0x0`, no support in ARM1176JZF-S processors.
[11:8]	-	Indicates support for level one cache line maintenance operations by Set/Way, Harvard architecture. `0x3`, ARM1176JZF-S processors support: clean data cache line by Set/Way clean and invalidate data cache line by Set/Way invalidate data cache line by Set/Way invalidate instruction cache line by Set/Way.
[7:4]	-	Indicates support for level one cache line maintenance operations by MVA, unified architecture. 0, no support in ARM1176JZF-S processors.
[3:0]	-	Indicates support for level one cache line maintenance operations by MVA, Harvard architecture. `0x2`, ARM1176JZF-S processors support: clean data cache line by MVA invalidate data cache line by MVA invalidate instruction cache line by MVA clean and invalidate data cache line by MVA invalidation of branch target buffer by MVA.

Table 3.23 lists the results of attempted access for each mode.

Table 3.23. Results of access to the Memory Model Feature Register 1

Secure Privileged		Non-secure Privileged		User
Read	Write	Read	Write	User
Data	Undefined exception	Data	Undefined exception	Undefined exception

To use the Memory Model Feature Register 1 read CP15 with:

Opcode_1 set to 0
CRn set to c0
CRm set to c1
Opcode_2 set to 5.

For example:

MRC p15, 0, <Rd>, c0, c1, 5 ;Read Memory Model Feature Register 1.

c0, Memory Model Feature Register 2

The purpose of the Memory Model Feature Register 2 is to provide information about the memory model, memory management, cache support, and TLB operations of the processor.

The Memory Model Feature Register 2 is:

in CP15 c0
a 32-bit read-only register common to the Secure and Non-secure worlds
accessible in privileged modes only.

Figure 3.19 shows the bit arrangement for Memory Model Feature Register 2.

Figure 3.19. Memory Model Feature Register 2 format

Table 3.24 lists how the bit values correspond with the Memory Model Feature Register 2 functions.

Table 3.24. Memory Model Feature Register 2 bit functions

Bits	Field name	Function
[31:28]	-	Indicates support for a Hardware access flag. `0x0`, no support in ARM1176JZF-S processors.
[27:24]	-	Indicates support for Wait For Interrupt stalling. `0x1`, ARM1176JZF-S processors support Wait For Interrupt.
[23:20]	-	Indicates support for memory barrier operations. `0x2`, ARM1176JZF-S processors support: Data Synchronization Barrier Prefetch Flush Data Memory Barrier.
[19:16]	-	Indicates support for TLB maintenance operations, unified architecture. `0x2`, ARM1176JZF-S processors support: invalidate all entries invalidate TLB entry by MVA invalidate TLB entries by ASID match.
[15:12]	-	Indicates support for TLB maintenance operations, Harvard architecture. `0x2`, ARM1176JZF-S processors support: invalidate instruction and data TLB, all entries invalidate instruction TLB, all entries invalidate data TLB, all entries invalidate instruction TLB by MVA invalidate data TLB by MVA invalidate instruction and data TLB entries by ASID match invalidate instruction TLB entries by ASID match invalidate data TLB entries by ASID match.
[11:8]	-	Indicates support for cache maintenance range operations, Harvard architecture. `0x1`, ARM1176JZF-S processors support: invalidate data cache range by VA invalidate instruction cache range by VA clean data cache range by VA clean and invalidate data cache range by VA.
[7:4]	-	Indicates support for background prefetch cache range operations, Harvard architecture. `0x0`, no support in ARM1176JZF-S processors.
[3:0]	-	Indicates support for foreground prefetch cache range operations, Harvard architecture. `0x0`, no support in ARM1176JZF-S processors.

Table 3.25 lists the results of attempted access for each mode.

Table 3.25. Results of access to the Memory Model Feature Register 2

Secure Privileged		Non-secure Privileged		User
Read	Write	Read	Write	User
Data	Undefined exception	Data	Undefined exception	Undefined exception

To use the Memory Model Feature Register 2 read CP15 with:

Opcode_1 set to 0
CRn set to c0
CRm set to c1
Opcode_2 set to 6.

For example:

MRC p15, 0, <Rd>, c0, c1, 6 ;Read Memory Model Feature Register 2.

c0, Memory Model Feature Register 3

The purpose of the Memory Model Feature Register 3 is to provide information about the memory model, memory management, cache support, and TLB operations of the processor.

The Memory Model Feature Register 3 is:

in CP15 c0
a 32-bit read-only register common to the Secure and Non-secure worlds
accessible in privileged modes only.

Figure 3.20 shows the bit arrangement for Memory Model Feature Register 3.

Figure 3.20. Memory Model Feature Register 3 format

Table 3.26 lists how the bit values correspond with the Memory Model Feature Register 3 functions.

Table 3.26. Memory Model Feature Register 3 bit functions

Bits Field name Function

[31:8]

Bits	Field name	Function
[31:8]	-	Reserved. RAZ.
[7:4]	-	Support for hierarchical cache maintenance by MVA, all architectures `0x0`, no support in ARM1176JZF-S processors.
[3:0]	-	Support for hierarchical cache maintenance by Set/Way, all architectures. `0x0`, no support in ARM1176JZF-S processors.

Reserved. RAZ.

[7:4]

Support for hierarchical cache maintenance by MVA, all architectures

0x0, no support in ARM1176JZF-S processors.

[3:0]

Support for hierarchical cache maintenance by Set/Way, all architectures.

0x0, no support in ARM1176JZF-S processors.

Table 3.27 lists the results of attempted access for each mode.

Table 3.27. Results of access to the Memory Model Feature Register 3

Secure Privileged		Non-secure Privileged		User
Read	Write	Read	Write	User
Data	Undefined exception	Data	Undefined exception	Undefined exception

To use the Memory Model Feature Register 3 read CP15 with:

Opcode_1 set to 0
CRn set to c0
CRm set to c1
Opcode_2 set to 7.

For example:

MRC p15, 0, <Rd>, c0, c1, 7 ;Read Memory Model Feature Register 3.

c0, Instruction Set Attributes Register 0

The purpose of the Instruction Set Attributes Register 0 is to provide information about the instruction set that the processor supports beyond the basic set.

The Instruction Set Attributes Register 0 is:

in CP15 c0
a 32-bit read-only register common to the Secure and Non-secure worlds
accessible in privileged modes only.

Figure 3.21 shows the bit arrangement for Instruction Set Attributes Register 0.

Figure 3.21. Instruction Set Attributes Register 0 format

Table 3.28 lists how the bit values correspond with the Instruction Set Attributes Register 0 functions.

Table 3.28. Instruction Set Attributes Register 0 bit functions

Bits	Field name	Function
[31:28]	-	Reserved. RAZ.
[27:24]	-	Indicates support for divide instructions. `0x0`, no support in ARM1176JZF-S processors.
[23:20]	-	Indicates support for debug instructions. `0x1`, ARM1176JZF-S processors support BKPT.
[19:16]	-	Indicates support for coprocessor instructions. `0x4`, ARM1176JZF-S processors support: CDP, LDC, MCR, MRC, STC CDP2, LDC2, MCR2, MRC2, STC2 MCRR, MRRC MCRR2, MRRC2.
[15:12]	-	Indicates support for combined compare and branch instructions. `0x0`, no support in ARM1176JZF-S processors.
[11:8]	-	Indicates support for bitfield instructions. `0x0`, no support in ARM1176JZF-S processors.
[7:4]	-	Indicates support for bit counting instructions. `0x1`, ARM1176JZF-S processors support CLZ.
[3:0]	-	Indicates support for atomic load and store instructions. `0x1`, ARM1176JZF-S processors support SWP and SWPB.

Table 3.29 lists the results of attempted access for each mode.

Table 3.29. Results of access to the Instruction Set Attributes Register 0

Secure Privileged		Non-secure Privileged		User
Read	Write	Read	Write	User
Data	Undefined exception	Data	Undefined exception	Undefined exception

To use the Instruction Set Attributes Register 0 read CP15 with:

Opcode_1 set to 0
CRn set to c0
CRm set to c2
Opcode_2 set to 0.

For example:

MRC p15, 0, <Rd>, c0, c2, 0 ;Read Instruction Set Attributes Register 0

c0, Instruction Set Attributes Register 1

The purpose of the Instruction Set Attributes Register 1 is to provide information about the instruction set that the processor supports beyond the basic set.

The Instruction Set Attributes Register 1 is:

in CP15 c0
a 32-bit read-only register common to the Secure and Non-secure worlds
accessible in privileged modes only.

Figure 3.22 shows the bit arrangement for Instruction Set Attributes Register 1.

Figure 3.22. Instruction Set Attributes Register 1 format

Table 3.30 lists how the bit values correspond with the Instruction Set Attributes Register 1 functions.

Table 3.30. Instruction Set Attributes Register 1 bit functions

Bits	Field name	Function
[31:28]	-	Indicates support for Java instructions. `0x1`, ARM1176JZF-S processors support BXJ and J bit in PSRs.
[27:24]	-	Indicates support for interworking instructions. `0x2`, ARM1176JZF-S processors support: BX, and T bit in PSRs BLX, and PC loads have BX behavior.
[23:20]	-	Indicates support for immediate instructions. `0x0`, no support in ARM1176JZF-S processors.
[19:16]	-	Indicates support for if then instructions. `0x0`, no support in ARM1176JZF-S processors.
[15:12]	-	Indicates support for sign or zero extend instructions. `0x2`, ARM1176JZF-S processors support: SXTB, SXTB16, SXTH, UXTB, UXTB16, and UXTH SXTAB, SXTAB16, SXTAH, UXTAB, UXTAB16, and UXTAH.
[11:8]	-	Indicates support for exception 2 instructions. `0x1`, ARM1176JZF-S processors support SRS, RFE, and CPS.
[7:4]	-	Indicates support for exception 1 instructions. `0x1`, ARM1176JZF-S processors support LDM(2), LDM(3) and STM(2).
[3:0]	-	Indicates support for endianness control instructions. `0x1`, ARM1176JZF-S processors support SETEND and E bit in PSRs.

Table 3.31 lists the results of attempted access for each mode.

Table 3.31. Results of access to the Instruction Set Attributes Register 1

Secure Privileged		Non-secure Privileged		User
Read	Write	Read	Write	User
Data	Undefined exception	Data	Undefined exception	Undefined exception

To use the Instruction Set Attributes Register 1 read CP15 with:

Opcode_1 set to 0
CRn set to c0
CRm set to c2
Opcode_2 set to 1.

For example:

MRC p15, 0, <Rd>, c0, c2, 1 ;Read Instruction Set Attributes Register 1

c0, Instruction Set Attributes Register 2

The purpose of the Instruction Set Attributes Register 2 is to provide information about the instruction set that the processor supports beyond the basic set.

The Instruction Set Attributes Register 2 is:

in CP15 c0
a 32-bit read-only register common to the Secure and Non-secure worlds
accessible in privileged modes only.

Figure 3.23 shows the bit arrangement for Instruction Set Attributes Register 2.

Figure 3.23. Instruction Set Attributes Register 2 format

Table 3.32 lists how the bit values correspond with the Instruction Set Attributes Register 2 functions.

Table 3.32. Instruction Set Attributes Register 2 bit functions

Bits	Field name	Function
[31:28]	-	Indicates support for reversal instructions. `0x1`, ARM1176JZF-S processors support REV, REV16, and REVSH.
[27:24]	-	Indicates support for PSR instructions. `0x1`, ARM1176JZF-S processors support MRS and MSR exception return instructions for data-processing.
[23:20]	-	Indicates support for advanced unsigned multiply instructions. `0x2`, ARM1176JZF-S processors support: UMULL and UMLAL UMAAL.
[19:16]	-	Indicates support for advanced signed multiply instructions. `0x3`, ARM1176JZF-S processors support: SMULL and SMLAL SMLABB, SMLABT, SMLALBB,SMLALBT, SMLALTB, SMLALTT, SMLATB, SMLATT, SMLAWB, SMLAWT, SMULBB, SMULBT, SMULTB, SMULTT, SMULWB, SMULWT, and Q flag in PSRs SMLAD, SMLADX, SMLALD, SMLALDX, SMLSD, SMLSDX, SMLSLD, SMLSLDX, SMMLA, SMMLAR, SMMLS, SMMLSR, SMMUL, SMMULR, SMUAD, SMUADX, SMUSD, and SMUSDX.
[15:12]	-	Indicates support for multiply instructions. `0x1`, ARM1176JZF-S processors support MLA.
[11:8]	-	Indicates support for multi-access interruptible instructions. `0x1`, ARM1176JZF-S processors support restartable LDM and STM.
[7:4]	-	Indicates support for memory hint instructions. `0x2`, ARM1176JZF-S processors support PLD.
[3:0]	-	Indicates support for load and store instructions. `0x1`, ARM1176JZF-S processors support LDRD and STRD.

Table 3.33 lists the results of attempted access for each mode.

Table 3.33. Results of access to the Instruction Set Attributes Register 2

Secure Privileged		Non-secure Privileged		User
Read	Write	Read	Write	User
Data	Undefined exception	Data	Undefined exception	Undefined exception

To use the Instruction Set Attributes Register 2 read CP15 with:

Opcode_1 set to 0
CRn set to c0
CRm set to c2
Opcode_2 set to 2.

For example:

MRC p15, 0, <Rd>, c0, c2, 2 ;Read Instruction Set Attributes Register 2

c0, Instruction Set Attributes Register 3

The purpose of the Instruction Set Attributes Register 3 is to provide information about the instruction set that the processor supports beyond the basic set.

The Instruction Set Attributes Register 3 is:

in CP15 c0
a 32-bit read-only registers common to the Secure and Non-secure worlds
accessible in privileged modes only.

Figure 3.24 shows the bit arrangement for Instruction Set Attributes Register 3.

Figure 3.24. Instruction Set Attributes Register 3 format

Table 3.34 lists how the bit values correspond with the Instruction Set Attributes Register 3 functions.

Table 3.34. Instruction Set Attributes Register 3 bit functions

Bits	Field name	Function
[31:28]	-	Indicates support for Thumb-2 extensions. `0x0`, no support in ARM1176JZF-S processors.
[27:24]	-	Indicates support for true NOP instructions. `0x1`, ARM1176JZF-S processors support NOP and the capability for additional NOP compatible hints. ARM1176JZF-S processors do not support NOP16.
[23:20]	-	Indicates support for Thumb copy instructions. `0x1`, ARM1176JZF-S processors support Thumb MOV(3) low register ⇒ low register, and the CPY alias for Thumb MOV(3).
[19:16]	-	Indicates support for table branch instructions. `0x0`, no support in ARM1176JZF-S processors.
[15:12]	-	Indicates support for synchronization primitive instructions. `0x2`, ARM1176JZF-S processors support: LDREX and STREX LDREXB, LDREXH, LDREXD, STREXB, STREXH, STREXD, and CLREX
[11:8]	-	Indicates support for SVC instructions. `0x1`, ARM1176JZF-S processors support SVC.
[7:4]	-	Indicates support for Single Instruction Multiple Data (SIMD) instructions. `0x3`, ARM1176JZF-S processors support: PKHBT, PKHTB, QADD16, QADD8, QADDSUBX, QSUB16, QSUB8, QSUBADDX, SADD16, SADD8, SADDSUBX, SEL, SHADD16, SHADD8, SHADDSUBX, SHSUB16, SHSUB8, SHSUBADDX, SSAT, SSAT16, SSUB16, SSUB8, SSUBADDX, SXTAB16, SXTB16, UADD16, UADD8, UADDSUBX, UHADD16, UHADD8, UHADDSUBX, UHSUB16, UHSUB8, UHSUBADDX, UQADD16, UQADD8, UQADDSUBX, UQSUB16, UQSUB8, UQSUBADDX, USAD8, USADA8, USAT, USAT16, USUB16, USUB8, USUBADDX, UXTAB16, UXTB16, and the GE[3:0] bits in the PSRs.
[3:0]	-	Indicates support for saturate instructions. `0x1`, ARM1176JZF-S processors support QADD, QDADD, QDSUB, QSUB and Q flag in PSRs.

Table 3.35 lists the results of attempted access for each mode.

Table 3.35. Results of access to the Instruction Set Attributes Register 3

Secure Privileged		Non-secure Privileged		User
Read	Write	Read	Write	User
Data	Undefined exception	Data	Undefined exception	Undefined exception

To use the Instruction Set Attributes Register 3 read CP15 with:

Opcode_1 set to 0
CRn set to c0
CRm set to c2
Opcode_2 set to 3.

For example:

MRC p15, 0, <Rd>, c0, c2, 3 ;Read Instruction Set Attributes Register 3

c0, Instruction Set Attributes Register 4

The purpose of the Instruction Set Attributes Register 4 is to provide information about the instruction set that the processor supports beyond the basic set.

The Instruction Set Attributes Register 4 is:

in CP15 c0
a 32-bit read-only register common to the Secure and Non-secure worlds
accessible in privileged modes only.

Figure 3.25 shows the bit arrangement for Instruction Set Attributes Register 4.

Figure 3.25. Instruction Set Attributes Register 4 format

Table 3.36 lists how the bit values correspond with the Instruction Set Attributes Register 4 functions.

Table 3.36. Instruction Set Attributes Register 4 bit functions

Bits	Field name	Function
[31:28]	-	Reserved. RAZ.
[27:24]	-	Reserved. RAZ.
[23:20]	-	Indicates fractional support for synchronization primitive instructions. `0x0`, ARM1176JZF-S processors support all synchronization primitive instructions. See Table 3.34.
[19:16]	-	Indicates support for barrier instructions. `0x0`, None. ARM1176JZF-S processors support only the CP15 barrier operations.
[15:12]	-	Indicates support for SMC instructions. `0x1`, ARM1176JZF-S processors support SMC.
[11:8]	-	Indicates support for writeback instructions. `0x1`, ARM1176JZF-S processors support all defined writeback addressing modes.
[7:4]	-	Indicates support for with shift instructions. `0x4`, ARM1176JZF-S processors support: shifts of loads and stores over the range LSL 0-3 constant shift options register controlled shift options.
[3:0]	-	Indicates support for Unprivileged instructions. `0x1`, ARM1176JZF-S processors support LDRBT, LDRT, STRBT, and STRT.

Table 3.37 lists the results of attempted access for each mode.

Table 3.37. Results of access to the Instruction Set Attributes Register 4

Secure Privileged		Non-secure Privileged		User
Read	Write	Read	Write	User
Data	Undefined exception	Data	Undefined exception	Undefined exception

To use the Instruction Set Attributes Register 4 read CP15 with:

Opcode_1 set to 0
CRn set to c0
CRm set to c2
Opcode_2 set to 4.

For example:

MRC p15, 0, <Rd>, c0, c2, 4 ;Read Instruction Set Attributes Register 4

c0, Instruction Set Attributes Register 5

The purpose of the Instruction Set Attributes Register 5 is to provide additional information about the properties of the processor.

The Instruction Set Attributes Register 5 is:

in CP15 c0
a 32-bit read-only registers common to the Secure and Non-secure worlds
accessible in privileged modes only.

The contents of the Instruction Set Attributes Register 5 are implementation defined. In the ARM1176JZF-S processor, Instruction Set Attributes Register 5 is read as 0x00000000.

Table 3.38 lists the results of attempted access for each mode.

Table 3.38. Results of access to the Instruction Set Attributes Register 5

Secure Privileged		Non-secure Privileged		User
Read	Write	Read	Write	User
Data	Undefined exception	Data	Undefined exception	Undefined exception

To use the Instruction Set Attributes Register 5 read CP15 with:

Opcode_1 set to 0
CRn set to c0
CRm set toc2
Opcode_2 set to 5.

For example:

MRC p15, 0, <Rd>, c0, c2, 5 ;Read Instruction Set Attribute Register 5.

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