ARM1176JZF-S Technical Reference Manual: 3.2.3. c0, Cache Type Register

3.2.3. c0, Cache Type Register

The purpose of the Cache Type Register is to provide information about the size and architecture of the cache for the operating system. This enables the operating system to establish how to clean the cache and how to lock it down. Inclusion of this register enables RTOS vendors to produce future-proof versions of their operating systems.

The Cache Type Register is:

in CP15 c0
a 32-bit read only register, common to Secure and Non-secure worlds
accessible in privileged modes only.

All ARMv4T and later cached processors contain this register. Figure 3.11 shows the arrangement of bits in the Cache Type Register.

Figure 3.11. Cache Type Register format

Table 3.6 lists how the bit values correspond with the Cache Type Register functions.

Table 3.6. Cache Type Register bit functions

Bits	Field name		Function
[31:29]	-		0
[28:25]	Ctype		The Cache type and Separate bits provide information about the cache architecture. b1110, indicates that the ARM1176JZF-S processor supports: write back cache Format C cache lockdown Register 7 cache cleaning operations.
[24]	S bit		S = 1, indicates that the processor has separate instruction and data caches and not a unified cache.
[23:12]	Dsize		Provides information about the size and construction of the Data cache. Note The ARM1176JZF-S processor does not support cache sizes of less than 4KB.
[23]		P bit	The P, Page, bit indicates restrictions on page allocation for bits [13:12] of the VA For ARM1176JZF-S processors, the P bit is set if the cache size is greater than 16KB. For more details see Restrictions on page table mappings page coloring. 0 = no restriction on page allocation. 1 = restriction applies to page allocation.
[22]		-	0
[21:18]		Size	The Size field indicates the cache size in conjunction with the M bit. b0000 = 0.5KB cache, not supported b0001 = 1KB cache, not supported b0010 = 2KB cache, not supported b0011 = 4KB cache b0100 = 8KB cache b0101 = 16KB cache b0110 = 32KB cache b0111 = 64KB cache b1000 = 128KB cache, not supported.
[17:15]		Assoc	b010, indicates that the ARM1176JZF-S processor has 4-way associativity. All other values for Assoc are reserved.
[14]		M bit	Indicates the cache size and cache associativity values in conjunction with the Size and Assoc fields. In the ARM1176JZF-S processor the M bit is set to 0, for the Data and Instruction Caches.
[13:12]		Len	b10, indicates that ARM1176JZF-S processor has a cache line length of 8 words, that is 32 bytes. All other values for Len are reserved.
[11:0]	Isize		Provides information about the size and construction of the Instruction cache.
[11]		P	The functions of the Isize bit fields are the same as the equivalent Dsize bit fields and the Isize values have the corresponding meanings.
[10]		-
[9:6]		Size
[5:3]		Assoc
[2]		M
[1:0]		Len

Table 3.7 lists the results of attempted access for each mode.

Table 3.7. Results of access to the Cache Type Register

Secure Privileged		Non-secure Privileged		User
Read	Write	Read	Write	User
Data	Undefined exception	Data	Undefined exception	Undefined exception

To use the Cache Type Register read CP15 with:

Opcode_1 set to 0
CRn set to c0
CRm set to c0
Opcode_2 set to 1.

For example:

MRC p15,0,<Rd>,c0,c0,1; returns cache details

Table 3.8, for example, lists the Cache Type Register values for an ARM1176JZF-S processor with:

separate instruction and data caches
cache size = 16KB
associativity = 4-way
line length = eight words
caches use write-back, CP15 c7 for cache cleaning, and Format C for cache lockdown.

Table 3.8. Example Cache Type Register format

Bits	Field name		Value	Behavior
[31:29]	Reserved		b000
[28:25]	Ctype		b1110
[24]	S		b1	Harvard cache
[23]	Dsize	P	b0
[22]		Reserved	b0
[21:18]		Size	b0101	16KB
[17:15]		Assoc	b010	4-way
[14]		M	b0
[13:12]		Len	b10	8 words per line, 32 bytes
[11]	Isize	P	b0
[10]		Reserved	b0
[9:6]		Size	b0101	16KB
[5:3]		Assoc	b010	4-way
[2]		M	b0
[1:0]		Len	b10	8 words per line, 32 bytes

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3.2.3. c0, Cache Type Register

Note