3.2.22. c7, Cache operations

The purpose of c7 is to:

Note

Cache operations also depend on:

The following cache operations globally flush the BTAC:

c7 consists of one 32-bit register that performs 28 functions. Figure 3.38 shows the arrangement of the 24 functions in this group that operate with the MCR and MRC instructions.

Figure 3.38. Cache operations


Figure 3.39 shows the arrangement of the 4 functions in this group that operate with the MCRR instruction.

Figure 3.39. Cache operations with MCRR instructions


Note

  • Writing c7 with a combination of CRm and Opcode_2 not listed in Figure 3.38 or CRm not listed in Figure 3.39 results in an Undefined exception apart from the following operations, that are architecturally defined as unified cache operations and have no effect:

    • MCR p15,0,<Rd>,c7,c7,{1-7}

    • MCR p15,0,<Rd>,c7,c11,{0-7}

    • MCR p15,0,<Rd>,c7,c15,{0-7}.

  • In the ARM1176JZF-S processor, reading from c7, except for reads from the Cache Dirty Status Register or PA Register, causes an Undefined instruction trap.

  • Writes to the Cache Dirty Status Register cause an Undefined exception.

  • If Opcode_1 = 0, these instructions are applied to a level one cache system. All other Opcode_1 values are reserved.

  • All accesses to c7 can only be executed in a privileged mode of operation, except Data Synchronization Barrier, Flush Prefetch Buffer, Data Memory Barrier, and Clean Data Cache Range. These can be operated in User mode. Attempting to execute a privileged instruction in User mode results in the Undefined instruction trap being taken.

There are three ways to use c7:

Invalidate, Clean, and Prefetch operations

The purposes of the invalidate, clean, and prefetch operations that c7 provides are to:

  • Invalidate part or all of the Data or Instruction caches

  • Clean part or all of the Data cache

  • Clean and Invalidate part or all of the Data cache

  • Prefetch code into the Instruction cache.

The terms used to describe the invalidate, clean, and prefetch operations are as defined in the Caches and Write Buffers chapter of the ARM Architecture Reference Manual.

For details of the behavior of c7 in the Secure and Non-secure worlds, see TrustZone behavior.

When it controls invalidate, clean, and prefetch operations c7 appears as a 32-bit write only register. There are four possible formats for the data that you write to the register that depend on the specific operation:

  • Set and Index format

  • MVA

  • VA

  • SBZ.

Set and Index format

Figure 3.40 shows the Set and Index format for invalidate and clean operations.

Figure 3.40. c7 format for Set and Index


Table 3.67 lists how the bit values correspond with the Cache Operation functions for Set and Index format operations.

Table 3.67. Functional bits of c7 for Set and Index

Bits

Field name

Function

[31:30]

Set

Selects the cache set to operate on, from the four cache sets.

Value is the cache set number.

[29:S+5]-UNP/SBZ.
[S+4:5]Index

Selects the cache line to operate on.

Value is the index number.

[4:1]-SBZ.
[0]0For the ARM1176JZF-S, this Should Be Zero.

The value of S in Table 3.68 depends on the cache size. Table 3.68 lists the relationship of cache sizes and S.

Table 3.68. Cache size and S parameter dependency

Cache sizeS
4KB5
8KB6
16KB7
32KB8
64KB9

The value of S is given by:

See c0, Cache Type Register for details of instruction and data cache size.

Note

If the data is stated to be Set and Index format, see Figure 3.40, it identifies the cache line that the operation applies to by specifying the cache Set that it belongs to and what its Index is within the Set. The Set corresponds to the number of the cache way, and the Index number corresponds to the line number within a cache way.

MVA format

Figure 3.41 shows the MVA format for invalidate, clean, and prefetch operations.

Figure 3.41. c7 format for MVA


Table 3.69 lists how the bit values correspond with the Cache Operation functions for MVA format operations.

Table 3.69. Functional bits of c7 for MVA

Bits

Field name

Function

[31:5]

MVA

Specifies address to invalidate, clean, or prefetch.

Holds the MVA of the cache line.

[4:0]-Ignored. This means that the lower 5 bits of MVA are ignored and these bits are not used for the cache operations. Only the top bits are necessary to determine whether or not the cache line is present in the cache. Even if the MVA is not aligned to the cache line, the cache operation is performed by ignoring the lower 5 bits.

Note

  • Invalidation and cleaning operations have no effect if they miss in the cache.

  • If the corresponding entry is not in the TLB, these instructions can cause a TLB miss exception or hardware page table walk, depending on the miss handling mechanism.

  • For the cache control operations, the MVAs that are passed to the cache are not translated by the FCSE extension.

VA format

Figure 3.42 shows the VA format for invalidate and clean operations. All VA format operations use the MCRR instruction.

Figure 3.42. Format of c7 for VA


Table 3.70 lists how the bit values correspond with the Cache Operation functions for VA format operations.

Table 3.70. Functional bits of c7 for VA format

Bits

Field name

Function

[31:5]

Virtual address

Specifies the start or end address to invalidate or clean.

Holds the true VA of the start or end of a memory block before any modification by FCSE.

[4:0]-SBZ.

You can perform invalidate, clean, and prefetch operations on:

  • single cache lines

  • entire caches

  • address ranges in cache.

Note

  • Clean, invalidate, and clean and invalidate operations apply regardless of the lock applied to entries.

  • An explicit flush of the relevant lines in the branch target cache must be performed after invalidation of Instruction Cache lines or the results are Unpredictable. There is no impact on security. This is not required after an entire Instruction Cache invalidation because the entire branch target cache is flushed automatically.

  • A small number of CP15 c7 operations can be executed by code while in User mode. Attempting to execute a privileged operation in User mode using CP15 c7 results in an Undefined instruction trap being taken.

To determine if the cache is dirty use the Cache Dirty Status Register, see Cache Dirty Status Register.

Entire cache

Table 3.71 lists the instructions and operations that you can use to clean and invalidate the entire cache.

Table 3.71. Cache operations for entire cache

Instruction

Data

Function

MCR p15, 0, <Rd>, c7, c5, 0

SBZ

Invalidate Entire Instruction Cache.

Also flushes the branch target cache and globally flushes the BTAC.

MCR p15, 0, <Rd>, c7, c6, 0

SBZ

Invalidate Entire Data Cache.

MCR p15, 0, <Rd>, c7, c7, 0

SBZ

Invalidate Both Caches.

Also flushes the branch target cache and globally flushes the BTAC.

MCR p15, 0, <Rd>, c7, c10, 0

SBZClean Entire Data Cache.
MCR p15, 0, <Rd>, c7, c14, 0SBZClean and Invalidate Entire Data Cache.

Register c7 specifies operations for cleaning the entire Data Cache, and also for performing a clean and invalidate of the entire Data Cache. These are blocking operations that can be interrupted. If they are interrupted, the R14 value that is captured on the interrupt is the address of the instruction that launched the cache clean operation + 4. This enables the standard return mechanism for interrupts to restart the operation.

If it is essential that the cache is clean, or clean and invalid, for a particular operation, the sequence of instructions for cleaning, or cleaning and invalidating, the cache for that operation must handle the arrival of an interrupt at any time when interrupts are not disabled. This is because interrupts can write to a previously clean cache. For this reason, the Cache Dirty Status Register indicates if the cache has been written to since the last clean of the cache was started, see Cache Dirty Status Register. You can interrogate the Cache Dirty Status Register to determine if the cache is clean, and if this is done while interrupts are disabled, the following operations can rely on having a clean cache. The following sequence shows this approach:

                             ; interrupts are assumed to be enabled at this point
                    Loop1    MOV R1, #0
                             MCR CP15, 0, R1, C7, C10, 0      ; Clean (or Clean & Invalidate) Cache
                             MRS R2, CPSR
                             CPSID iaf                        ; Disable interrupts
                             MRC CP15, 0, R1, C7, C10, 6      ; Read Cache Dirty Status Register
                             ANDS R1, R1, #1                  ; Check if it is clean
                             BEQ UseClean
                             MSR CPSR, R2                     ; Re-enable interrupts
                             B Loop1                          ; - clean the cache again
                    UseClean Do_Clean_Operations              ; Perform whatever operation relies on
                                                              ; the cache being clean/invalid. 
                                                              ; To reduce impact on interrupt
                                                              ; latency, this sequence should be
                                                              ; short
                             MSR CPSR, R2                     ; Re-enable interrupts

The long cache clean operation is performed with interrupts enabled throughout this routine.

Single cache lines

There are two ways to perform invalidate or clean operations on cache lines:

  • by use of Set and Index format

  • by use of MVA format.

Table 3.72 lists the instructions and operations that you can use for single cache lines.

Table 3.72. Cache operations for single lines

Instruction

Data

Function

MCR p15, 0, <Rd>, c7, c5, 1

MVA

Invalidate Instruction Cache Line, using MVA

MCR p15, 0, <Rd>, c7, c5, 2

Set/Index

Invalidate Instruction Cache Line, using Index

MCR p15, 0, <Rd>, c7, c6, 1

MVA

Invalidate Data Cache Line, using MVA

MCR p15, 0, <Rd>, c7, c6, 2Set/Index

Invalidate Data Cache Line, using Index

MCR p15, 0, <Rd>, c7, c10, 1

MVA

Clean Data Cache Line, using MVA

MCR p15, 0, <Rd>, c7, c10, 2

Set/Index

Clean Data Cache Line, using Index

MCR p15, 0, <Rd>, c7, c13, 1

MVA

Prefetch Instruction Cache Line

MCR p15, 0, <Rd>, c7, c14, 1

MVA

Clean and Invalidate Data Cache Line, using MVA

MCR p15, 0, <Rd>, c7, c14, 2

Set/Index

Clean and Invalidate Data Cache Line, using Index


Example 3.1 shows how to use Clean and Invalidate Data Cache Line with Set and Index to clean and invalidate one whole cache way, in this example, way 3. The example works with any cache size because it reads the cache size from the Cache Type Register.

Example 3.1. Clean and Invalidate Data Cache Line with Set and Index

                MRC     p15,0,R0,c0,c0,1       ; Read cache type reg
                AND     R0,R0,#0x1C0000        ; Extract D cache size
                MOV     R0,R0, LSR #18         ; Move to bottom bits
                ADD     R0,R0,#7               ; Get Index loop max
                MOV     r1,#3:SHL:30           ; Set up Set = 3
                MOV     R2,#0                  ; Set up Index counter
                MOV     R3,#1
                MOV     R3,R3, LSL R0          ; Set up Index loop max
index_loop
                ORR     R4,R2,r1               ; Set and Index format
                MCR     p15,0,R4,c7,c14,2      ; Clean&inval D cache line
                ADD     R2,R2,#1:SHL:5         ; Increment Index
                CMP     R2,R3                  ; Done all index values?
                BNE     index_loop             ; Loop until done

Address ranges

Table 3.73 lists the instructions and operations that you can use to clean and invalidate the address ranges in cache.

Table 3.73. Cache operations for address ranges

InstructionDataFunction

MCRR p15,0,<End Address>,<Start Address>,c5

VAInvalidate Instruction Cache Range

MCRR p15,0,<End Address>,<Start Address>,c6

VAInvalidate Data Cache Range

MCRR p15,0,<End Address>,<Start Address>,c12

VAClean Data Cache Range[a]

MCRR p15,0,<End Address>,<Start Address>,c14

VAClean and Invalidate Data Cache Range

[a] This operation is accessible in both User and privileged modes of operation. All other operations listed here are only accessible in privileged modes of operation.


The operations in Table 3.73 can only be performed using an MCRR or MCRR2 instruction, and all other operations to these registers are ignored.

The End Address and Start Address in Table 3.73 is the true VA before any modification by the Fast Context Switch Extension (FCSE). This address is translated by the FCSE logic. Each of the range operations operates between cache lines containing the Start Address and the End Address, inclusive of Start Address and End Address.

Because the least significant address bits are ignored, the transfer automatically adjusts to a line length multiple spanning the programmed addresses.

The Start Address is the first VA of the block transfer. It uses the VA bits [31:5]. The End Address is the VA where the block transfer stops. This address is at the start of the line containing the last address to be handled by the block transfer. It uses the VA bits [31:5].

If the Start Address is greater than the End Address the effect is architecturally Unpredictable. The ARM1176JZF-S processor does not perform cache operations in this case. All block transfers are interruptible. When Block transfers are interrupted, the R14 value that is captured is the address of the instruction that launched the block operation + 4. This enables the standard return mechanism for interrupts to restart the operation.

Exception behavior

The blocking block transfers cause a Data Abort on a translation fault if a valid page table entry cannot be fetched. The FAR indicates the address that caused the fault, and the DFSR indicates the reason for the fault.

TrustZone behavior

TrustZone affects cache operations as follows:

Secure world operations

In the Secure world cache operations can affect both Secure and Non-secure cache lines:

  • Clean, invalidate, and clean and invalidate operations affect all cache lines regardless of their status as locked or unlocked.

  • For clean, invalidate, and clean and invalidate operations with the Set and Index format, the selected cache line is affected regardless of the Secure tag.

  • For MVA operations clean, invalidate, and clean and invalidate:

    • when the MVA is marked as Non-secure in the page table, only Non-secure entries are affected

    • when the MVA is marked as Secure in the page table, only Secure entries are affected.

Non-secure world operations

In the Non-secure world:

  • Clean, invalidate, and clean and invalidate operations only affect Non-secure cache lines regardless of the method used.

  • Any attempt to access Secure cache lines is ignored.

  • Invalidate Entire Data Cache and Invalidate Both Caches operations cause an Undefined exception. This prevents invalidating lockdown entries that might be configured as Secure.

    • the Invalidate Both Caches operation globally flushes the BTAC.

  • Invalidate Entire Instruction Cache operations:

    • cause an Undefined exception if lockdown entries are reserved for the Secure world

    • affect all Secure and Non-secure cache entries if the lockdown entries are not reserved for the Secure world

    • globally flush the BTAC.

Cache Dirty Status Register

The purpose of the Cache Dirty Status Register is to indicate when the Cache is dirty.

The Cache Dirty Status Register is:

  • in CP15 c7

  • a 32-bit read only register, banked for Secure and Non-secure worlds

  • accessible in privileged modes only.

Figure 3.43 shows the arrangement of bits in the Cache Dirty Status Register.

Figure 3.43. Cache Dirty Status Register format


Table 3.74 lists how the bit value corresponds with the Cache Dirty Status Register function.

Table 3.74. Cache Dirty Status Register bit functions

Bits

Field name

Function

[31:1]

-UNP/SBZ.
[0]C

The C bit indicates if the cache is dirty.

0 = indicates that no write has hit the cache since the last cache clean, clean and invalidate, or invalidate all operation, or reset, successfully left the cache clean. This is the reset value.

1 = indicates that the cache might contain dirty data.


The Cache Dirty Status Register behaves in this way with regard to the Secure and Non-secure cache:

  • clean, invalidate, and clean and invalidate operations of the whole cache in the Non-secure world clear the Non-secure Cache Dirty Status Register

  • clear, invalidate, and clean and invalidate operations of the whole cache in the Secure world clear both the Secure and Non-secure Cache Dirty Status Registers

  • if the core is in the Non-secure world or targets Non-secure data from the Secure world, stores that write a dirty bit in the cache set both the Secure and the Non-secure Cache Dirty Status Register

  • all stores that write a dirty bit in the cache set the Secure Cache Dirty Status Register.

All writes and User mode reads of the Cache Dirty Status Register cause an Undefined exception.

To use the Cache Dirty Status Register read CP15 with:

  • Opcode_1 set to 0

  • CRn set to c7

  • CRm set to c10

  • Opcode_2 set to 6.

For example:

MRC p15, 0, <Rd>, c7, c10, 6    ; Read Cache Dirty Status Register.

Flush operations

Table 3.75 lists the flush operations and instructions available through c7.

Table 3.75. Cache operations flush functions

Instruction

Data

Function

MCR p15, 0, <Rd>, c7, c5, 4SBZFlush Prefetch Buffer[a].
MCR p15, 0, <Rd>, c7, c5, 6SBZFlush Entire Branch Target Cache[b].
MCR p15, 0, <Rd>, c7, c5, 7MVA[c]Flush Branch Target Cache Entry with MVA.

[a] These operations are accessible in both User and privileged modes of operation. All other operations are only accessible in privileged modes of operation.

[b] This operation is accessible in both Privileged and User modes of operation when in Debug state.

[c] The range of MVA bits used in this function is different to the range of bits used in other functions that have MVA data.


The Flush Branch Target Entry using MVA operation uses a different MVA format to that used by Clean and Invalidate operations. Figure 3.44 shows the MVA format for the Flush Branch Target Entry operation.

Figure 3.44. c7 format for Flush Branch Target Entry using MVA


Table 3.76 lists how the bit values correspond with the Flush Branch Target Entry using MVA functions.

Table 3.76. Flush Branch Target Entry using MVA bit functions

BitsField nameFunction
[31:3]MVA

Specifies address to flush.

Holds the MVA of the Branch Target Cache line.

[2:0]-SBZ.

Note

The MVA does not have to be cache line aligned.

Flushing the prefetch buffer has the effect that all instructions occurring in program order after this instruction are fetched from the memory system after the execution of this instruction, including the level one cache or TCM. This operation is useful for ensuring the correct execution of self-modifying code. See Explicit Memory Barriers.

VA to PA translation operations

The purpose of the VA to PA translation operations is to provide a Secure means to determine address translation in the Secure and Non-secure worlds and for address translation between the Secure and Non-secure worlds. VA to PA translations operate through:

PA Register

The purpose of the PA Register is to hold:

  • the PA after a successful translation

  • the source of the abort for an unsuccessful translation.

Table 3.77 lists the purpose of the bits of the PA Register for successful translations and Table 3.78 lists the purpose of the bits of the PA Register for unsuccessful translations.

The PA Register is:

  • in CP15 c7

  • a 32 bit read/write register banked in Secure and Non-secure worlds

  • accessible in privileged modes only.

Figure 3.45 shows the format of the PA Register for successful translations.

Figure 3.45. PA Register format for successful translation


Figure 3.46 shows the format of the PA register for aborted translations.

Figure 3.46. PA Register format for aborted translation


Table 3.77 lists the functional bits of the PA Register for successful translation.

Table 3.77. PA Register for successful translation bit functions

BitsField nameFunction
[31:10]PAPA Translated physical address.
[9]NS

Indicates the state of the NS Attribute bit in the page table:

0 = Secure memory

1 = Non-secure memory.

[8]P

Not used in the ARM1176JZF-S processor.

UNP/SBZ.

[7]SH

Indicates shareable memory:

0 = Non-shared

1 = Shared.

[6:4]INNER

Indicates the inner attributes from the page table:

b000 = Noncacheable

b001 = Strongly Ordered

b010 = Reserved

b011 = Device

b100 = Reserved

b101 = Reserved

b110 = Inner Write-through, no allocate on write

b111 = Inner Write-back, no allocate on write.

[3:2]OUTER

Indicates the outer attributes from the page table:

b00 = Noncacheable

b01 = Write-back, allocate on write

b10 = Write-through, no allocate on write

b11 = Write-back, no allocate on write.

[1]-

Reserved.

UNP/SBZ.

[0]-

Indicates that the translation succeeded:

0 = Translation successful.


Table 3.78 lists the functional bits of the PA Register for aborted translation.

Table 3.78. PA Register for unsuccessful translation bit functions

BitsField nameFunction
[31:7]-UNP/SBZ.
[6:1]FSR[12,10,3:0]

Holds the FSR bits for the aborted address, see c5, Data Fault Status Register and c5, Instruction Fault Status Register.

FSR bits [12], [10], and [3:0].

[0]-

Indicates that the translation aborted:

1 = Translation aborted.


Attempts to access the PA Register in User mode results in an Undefined exception.

Note

The VA to PA translation can only generate an abort to the core if the operation failed because an external abort occurred on the possible page table request. In this case, the processor updates the Secure or Non-secure version of the PA register, depending on the Secure or Non-secure state of the core when the operation was issued. The processor also updates the Data Fault Status Register and the Fault Address Register:

  • if the EA bit in the Secure Configuration Register is set, the Secure versions of the two registers are updated and the processor traps the abort into Secure Monitor mode

  • if the EA bit in the Secure Configuration Register is not set, the processor updates the Secure or Non-secure versions of the two registers, depending on the Secure or Non-secure state of the core when the operation was issued.

For all other cases when the VA to PA operation fails, the processor only updates the PA register, Secure or Non-secure version, depending on the Secure or Non-secure state of the core when the operation was issued, with the Fault Status Register encoding and bit[0] set. The Data Fault Status Register and Fault Address Register remain unchanged and the processor does not send an abort to the core.

To use the PA Register read or write CP15 c7 with:

  • Opcode_1 set to 0

  • CRn set to c7

  • CRm set to c4

  • Opcode_2 set to 0.

For example:

MRC p15, 0, <Rd>, c7, c4, 0    ; Read PA Register
MCR p15, 0, <Rd>, c7, c4, 0    ; Write PA Register
VA to PA translation in the current world

The purpose of the VA to PA translation in the current world is to translate the address with the current virtual mapping for either Secure or Non-secure worlds.

The VA to PA translation in the current world operations use:

  • CP15 c7

  • four, 32-bit write-only operations common to the Secure and Non-secure worlds

  • operations accessible in privileged modes only

The operations work for privileged or User access permissions and returns information in the PA Register for aborts, when the translation is unsuccessful, or page table information, when the translation succeeds.

Attempts to access the VA to PA translation operations in the current world in User mode result in an Undefined exception.

To use the VA to PA translation in the current world write CP15 c7 with:

  • Opcode_1 set to 0

  • CRn set to c7

  • CRm set to c8

  • Opcode_2 set to:

    • 0 for privileged read permission

    • 1 for privileged write permission

    • 2 for User read permission

    • 3 for User write permission.

General register <Rn> contains the VA for translation. The result returns in the PA Register, for example:

MCR p15,0,<Rn>,c7,c8,3        ;get VA = <Rn> and run VA-to-PA translation
                              ;with User write permission.
                              ;if the selected page table has the 
                              ;User write permission, the PA is loaded
                              ;in PA register, otherwise abort information is
                              ;loaded in PA Register
MRC p15,0,<Rd>,c7,c4,0        ;read in <Rd> the PA value

Note

The VA that this operation uses is the true VA not the MVA.

VA to PA translation in the other world

The purpose of the VA to PA translation in the other world is to translate the address with the current virtual mapping in the Non-secure world while the core is in the Secure world.

The VA to PA translation in the other world operations use:

  • CP15 c7

  • four, 32-bit write-only operations in the Secure world only

  • operations accessible in privileged modes only.

The operations work in the Secure world for Non-secure privileged or Non-secure User access permissions and returns information in the PA Register for aborts, when the translation is unsuccessful, or page table information, when the translation succeeds.

Attempts to access the VA to PA translation operations in the other world in any Non-secure or User mode result in an Undefined exception.

To use the VA to PA translation in the other world write CP15 c7 with:

  • Opcode_1 set to 0

  • CRn set to c7

  • CRm set to c8

  • Opcode_2 set to:

    • 4 for privileged read permission

    • 5 for privileged write permission

    • 6 for User read permission

    • 7 for User write permission.

General register <Rn> contains the VA for translation. The result returns in the PA Register, for example:

MCR p15,0,<Rn>,c7,c8,4          ;get VA = <Rn> and run Non-secure translation
                                ;with Non-secure privileged read permission.
                                ;if the selected page table has the 
                                ;privileged read permission, the PA is loaded
                                ;in PA register, otherwise abort information is
                                ;loaded in PA Register
MRC p15,0,<Rd>,c7,c4,0          ;read in <Rd> the PA value

Data Synchronization Barrier operation

The purpose of the Data Synchronization Barrier operation is to ensure that all outstanding explicit memory transactions complete before any following instructions begin. This ensures that data in memory is up to date before the processor executes any more instructions.

Note

The Data Synchronization Barrier operation is synonymous with Drain Write Buffer and Data Write Barrier in earlier versions of the architecture.

The Data Synchronization Barrier operation is:

  • in CP15 c7

  • 32-bit write-only access, common to both Secure and Non-secure worlds

  • accessible in both User and Privileged modes.

Table 3.79 lists the results of attempted access for each mode.

Table 3.79. Results of access to the Data Synchronization Barrier operation

ReadWrite
Undefined exceptionData

To use the Data Memory Barrier operation write CP15 with <Rd> SBZ and:

  • Opcode_1 set to 0

  • CRn set to c7

  • CRm set to c10

  • Opcode_2 set to 4.

For example:

MCR p15,0,<Rd>,c7,c10,4    ; Data Synchronization Barrier operation.

For more details, see Explicit Memory Barriers.

Note

The W bit that usually enables the Write Buffer is not implemented in ARM1176JZF-S processors, see c1, Control Register.

This instruction acts as an explicit memory barrier. This instruction completes when all explicit memory transactions occurring in program order before this instruction are completed. No instructions occurring in program order after this instruction are executed until this instruction completes. Therefore, no explicit memory transactions occurring in program order after this instruction are started until this instruction completes. See Explicit Memory Barriers.

It can be used instead of Strongly Ordered memory when the timing of specific stores to the memory system has to be controlled. For example, when a store to an interrupt acknowledge location must be completed before interrupts are enabled.

The Data Synchronization Barrier operation can be performed in both privileged and User modes of operation.

Data Memory Barrier operation

The purpose of the Data Memory Barrier operation is to ensure that all outstanding explicit memory transactions complete before any following explicit memory transactions begin. This ensures that data in memory is up to date before any memory transaction that depends on it.

The Data Memory Barrier operation is:

  • in CP15 c7

  • a 32-bit write only operation, common to the Secure and Non-secure worlds

  • accessible in User and Privileged mode.

Table 3.80 lists the results of attempted access for each mode.

Table 3.80. Results of access to the Data Memory Barrier operation

ReadWrite
Undefined exceptionData

To use the Data Memory Barrier operation write CP15 with <Rd> SBZ and:

  • Opcode_1 set to 0

  • CRn set to c7

  • CRm set to c10

  • Opcode_2 set to 5.

For example:

MCR p15,0,<Rd>,c7,c10,5    ; Data Memory Barrier Operation.

For more details, see Explicit Memory Barriers.

Wait For Interrupt operation

The purpose of the Wait For Interrupt operation is to put the processor in to a low power state, see Standby mode.

The Wait For Interrupt operation is:

  • in CP15 c7

  • 32-bit write only access, common to Secure and Non-secure worlds

  • accessible in privileged modes only.

Table 3.81 lists the results of attempted access for each mode.

Table 3.81. Results of access to the Wait For Interrupt operation

Secure PrivilegedNon-secure PrivilegedUser
ReadWriteReadWrite
Undefined exceptionWait For InterruptUndefined exceptionWait For InterruptUndefined exception

To use the Wait For Interrupt operation write CP15 with <Rd> SBZ and:

  • Opcode_1 set to 0

  • CRn set to c7

  • CRm set to c0

  • Opcode_2 set to 4.

For example:

MCR p15,0,<Rd>,c7,c0,4    ; Wait For Interrupt.

This puts the processor into a low-power state and stops it executing following instructions until an interrupt, an imprecise external abort, or a debug request occurs, regardless of whether the interrupts or external imprecise aborts are disabled by the masks in the CPSR. When an interrupt does occur, the MCR instruction completes. If interrupts are enabled, the IRQ or FIQ handler is entered as normal. The return link in R14_irq or R14_fiq contains the address of the MCR instruction plus 8, so that the normal instruction used for interrupt return (SUBS PC,R14,#4) returns to the instruction following the MCR.

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